Re: [Gems-users] Flush back L2 Cache

[Milo Martin <milom@xxxxxxxxxxxxx>]

On Feb 10, 2005, at 3:32 PM, Weihang Jiang wrote:

> What I am asking is about memory replacement. When a physical memory
> page is replaced, the corresponding L2 cache lines need to be flushed
> first.

I'm not sure I understand what you're saying.  When a physical memory 
page is replaced, the TLB entry needs to change, but the blocks in the 
cache can stay where they are.  When the operating system actually 
swaps in the new page, the DMA controller will need to write the 
various blocks in the page.  These DMA writes are responsible for 
invalidating (or updating) any caches that might have readable copies 
of the block.  Currently, Ruby doesn't treat DMA writes in this way, 
but at one point we had a version that treated all DMA operations as 
happening on either a separate virtual processor or as all DMA 
happening at processor zero.  Simics gives us all of these requests, we 
currently just choose to ignore them.

Does that make sense, or am I misinterpreting the question?

- Milo

--
Milo M. K. Martin (milom@xxxxxxxxxxxxx)
http://www.cis.upenn.edu/~milom/
Assistant Professor
Computer and Information Sciences Department
University of Pennsylvania