Branch: refs/heads/bbiiggppiigg/fix-riscv-addr-width
Home: https://github.com/dyninst/dyninst
Commit: f44adbbe3d521e1cf07a95f750e84893feb37aa8
https://github.com/dyninst/dyninst/commit/f44adbbe3d521e1cf07a95f750e84893feb37aa8
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-05-31 (Sun, 31 May 2026)
Changed paths:
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix 64-bit jump target truncation in IA_riscv64::isMultiInsnJump
The resolved multi-instruction jump target from ConstantAST::val().val
(uint64_t) was funneled through a uint32_t local before being stored
into *target (Address*). On riscv64 any indirect-branch target above
4 GiB lost its high 32 bits, causing parsing to follow a bogus address.
Widen the local to Address so the full 64-bit target is preserved.
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
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