[DynInst_API:] [dyninst/dyninst] 315095: RISCV_GRP_ISRV64 -> RISCV_FEATURE_ISRV64

[Tim Haines <noreply@xxxxxxxxxx>]

  Branch: refs/heads/thaines/update_riscv_capstone
  Home:   https://github.com/dyninst/dyninst
  Commit: 3150959a14a2ac8826b029b0e4f91597ce091911
      https://github.com/dyninst/dyninst/commit/3150959a14a2ac8826b029b0e4f91597ce091911
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/categories.h

  Log Message:
  -----------
  RISCV_GRP_ISRV64 -> RISCV_FEATURE_ISRV64


  Commit: d5300c37f1287b142cd0599c61e9c9f67d054c13
      https://github.com/dyninst/dyninst/commit/d5300c37f1287b142cd0599c61e9c9f67d054c13
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/categories.h

  Log Message:
  -----------
  RISCV_GRP_ISRV32 -> RISCV_FEATURE_ISRV32


  Commit: 1a3334bc87bcc12fdcfe89d193c292733acde234
      https://github.com/dyninst/dyninst/commit/1a3334bc87bcc12fdcfe89d193c292733acde234
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/categories.h

  Log Message:
  -----------
  RISCV_REG_ZERO -> RISCV_REG_X0


  Commit: 5cd38e2dd78aa930cd3da1deb34d0739e7e1641c
      https://github.com/dyninst/dyninst/commit/5cd38e2dd78aa930cd3da1deb34d0739e7e1641c
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/categories.h
    M instructionAPI/src/decoder/riscv/decoder.C

  Log Message:
  -----------
  RISCV_REG_RA -> RISCV_REG_X1


  Commit: a334ecd4d359242ccc984d2f6c6675bf5374453a
      https://github.com/dyninst/dyninst/commit/a334ecd4d359242ccc984d2f6c6675bf5374453a
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/register_xlat.C

  Log Message:
  -----------
  RISCV_REG_F<N>_32 -> RISCV_REG_F<N>_F


  Commit: 39ebe2480f221a5eeb5dfa419ebeeb92d86e2b7f
      https://github.com/dyninst/dyninst/commit/39ebe2480f221a5eeb5dfa419ebeeb92d86e2b7f
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/register_xlat.C

  Log Message:
  -----------
  RISCV_REG_F<N>_64 -> RISCV_REG_F<N>_D


  Commit: 66326cd5d84c4578c741ec99261fde9baeab58d8
      https://github.com/dyninst/dyninst/commit/66326cd5d84c4578c741ec99261fde9baeab58d8
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/opcode_xlat.C

  Log Message:
  -----------
  RISCV_INS_AMOADD_X_AQ_RL -> RISCV_INS_AMOADD_X_AQRL


  Commit: df2a15676223078c6a5e3abdd891098bb2323430
      https://github.com/dyninst/dyninst/commit/df2a15676223078c6a5e3abdd891098bb2323430
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M common/h/mnemonics/riscv64_entryIDs.h
    M dataflowAPI/src/convertOpcodes.C
    M instructionAPI/src/decoder/riscv/opcode_xlat.C

  Log Message:
  -----------
  Remove uret instruction

It seems like Capstone no longer supports it.


  Commit: 7277c063ca46c52ccb941b31b39ad7b7b0330114
      https://github.com/dyninst/dyninst/commit/7277c063ca46c52ccb941b31b39ad7b7b0330114
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/decoder.C

  Log Message:
  -----------
  RISCV_REG_ZERO -> RISCV_REG_X0


  Commit: 1bbb5c1f4309e826a8f5bf2bfdc2930aa80acbea
      https://github.com/dyninst/dyninst/commit/1bbb5c1f4309e826a8f5bf2bfdc2930aa80acbea
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/decoder.C

  Log Message:
  -----------
  CS_MODE_RISCVC -> CS_MODE_RISCV_C


  Commit: 8cf71ff34544652f827bf2d96ee4f4dfa42b8bd9
      https://github.com/dyninst/dyninst/commit/8cf71ff34544652f827bf2d96ee4f4dfa42b8bd9
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2026-05-07 (Thu, 07 May 2026)

  Changed paths:
    M instructionAPI/src/decoder/riscv/decoder.C

  Log Message:
  -----------
  Add placeholders for RISCV_OP_FP, RISCV_OP_CSR


Compare: https://github.com/dyninst/dyninst/compare/7a038c215e32...8cf71ff34544

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