Branch: refs/heads/angushe/riscv
Home: https://github.com/dyninst/dyninst
Commit: e1df9eb4e0a486f86fbb33f642ed512f73f302ab
https://github.com/dyninst/dyninst/commit/e1df9eb4e0a486f86fbb33f642ed512f73f302ab
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: 4beee28378a08d37fc0ac95469b938ab5c93fc09
https://github.com/dyninst/dyninst/commit/4beee28378a08d37fc0ac95469b938ab5c93fc09
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: 8c352e114f8dc112e172bc2621a31dba94a6680b
https://github.com/dyninst/dyninst/commit/8c352e114f8dc112e172bc2621a31dba94a6680b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: 5e47f8f5819c4da0bb26817dbc431dcaa650a883
https://github.com/dyninst/dyninst/commit/5e47f8f5819c4da0bb26817dbc431dcaa650a883
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: 2b6331f7f70666ec4f7fd46adbdd6e127cb1c8e7
https://github.com/dyninst/dyninst/commit/2b6331f7f70666ec4f7fd46adbdd6e127cb1c8e7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: a11c31b752f31f1411fde6e4fd79958f4de815a2
https://github.com/dyninst/dyninst/commit/a11c31b752f31f1411fde6e4fd79958f4de815a2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: 67dccfc90ab357421a6118277144e78336a6d359
https://github.com/dyninst/dyninst/commit/67dccfc90ab357421a6118277144e78336a6d359
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 998f38bf542ffb99d05939d2c415ab2cbe074077
https://github.com/dyninst/dyninst/commit/998f38bf542ffb99d05939d2c415ab2cbe074077
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: 88a65891666bd7b91268a312484ab4e51f3a7761
https://github.com/dyninst/dyninst/commit/88a65891666bd7b91268a312484ab4e51f3a7761
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: 81844c6456e1331b9143a196cb75ad4ba6b93a5b
https://github.com/dyninst/dyninst/commit/81844c6456e1331b9143a196cb75ad4ba6b93a5b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: 796c61186abe6d8ec9754a6fb500cd2f79a5fed3
https://github.com/dyninst/dyninst/commit/796c61186abe6d8ec9754a6fb500cd2f79a5fed3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 141df970e10cbb00daae329de79aab8acd470521
https://github.com/dyninst/dyninst/commit/141df970e10cbb00daae329de79aab8acd470521
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: f9b6cc28d6244a2cdae0e3ce2b7bf2a23e820f49
https://github.com/dyninst/dyninst/commit/f9b6cc28d6244a2cdae0e3ce2b7bf2a23e820f49
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: 20835af02fa9be9526cb9db22fccd8676a94fb13
https://github.com/dyninst/dyninst/commit/20835af02fa9be9526cb9db22fccd8676a94fb13
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: d5dc3f39627545e7a1b3b1caa0f8a7b27315ebea
https://github.com/dyninst/dyninst/commit/d5dc3f39627545e7a1b3b1caa0f8a7b27315ebea
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: 9c687048bdf9fe0ba495b99de39cfd3184b0d80d
https://github.com/dyninst/dyninst/commit/9c687048bdf9fe0ba495b99de39cfd3184b0d80d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: 03d5ee8e7420967ba3e2ec3dd6884ce5c3acce89
https://github.com/dyninst/dyninst/commit/03d5ee8e7420967ba3e2ec3dd6884ce5c3acce89
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: bedb3a9e7b8899693a72978d840dbb7e7f55ea08
https://github.com/dyninst/dyninst/commit/bedb3a9e7b8899693a72978d840dbb7e7f55ea08
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: ef95e7ffaecb89474a67f6ca3a2f4abb05ce5f44
https://github.com/dyninst/dyninst/commit/ef95e7ffaecb89474a67f6ca3a2f4abb05ce5f44
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: 7559afb4a258274aaa6dbeb96cd8e2a3d8f6accb
https://github.com/dyninst/dyninst/commit/7559afb4a258274aaa6dbeb96cd8e2a3d8f6accb
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: bfa220cc2c6004f3fd55ab2948d32201a011292a
https://github.com/dyninst/dyninst/commit/bfa220cc2c6004f3fd55ab2948d32201a011292a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: 8da2ffb6573ef236803ae6ea7ead497f93714de7
https://github.com/dyninst/dyninst/commit/8da2ffb6573ef236803ae6ea7ead497f93714de7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: 60b7bad7537f0f46871b66a45f332901231b33d6
https://github.com/dyninst/dyninst/commit/60b7bad7537f0f46871b66a45f332901231b33d6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: 6c696e9f91e223dc8b7b04628300dfa2cd1403b5
https://github.com/dyninst/dyninst/commit/6c696e9f91e223dc8b7b04628300dfa2cd1403b5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: 9f19c937e43597a58c974cc3d2a8e25892c82d76
https://github.com/dyninst/dyninst/commit/9f19c937e43597a58c974cc3d2a8e25892c82d76
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: f53e35d84845f7299a95411f47250f1a8ca662dd
https://github.com/dyninst/dyninst/commit/f53e35d84845f7299a95411f47250f1a8ca662dd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: 4877d32f87431cafc351ab949ec4346a96ce71ae
https://github.com/dyninst/dyninst/commit/4877d32f87431cafc351ab949ec4346a96ce71ae
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: bb539e889dafc2bfb1d2d59a73a2b13060b66b43
https://github.com/dyninst/dyninst/commit/bb539e889dafc2bfb1d2d59a73a2b13060b66b43
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: 80c35a43b9f017a741659bf78a0890542399266d
https://github.com/dyninst/dyninst/commit/80c35a43b9f017a741659bf78a0890542399266d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: e6df3fd60ed1037200d2f810bd7ca9978d1f28d0
https://github.com/dyninst/dyninst/commit/e6df3fd60ed1037200d2f810bd7ca9978d1f28d0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: a5871968d646bb6ac156f03e01f60c363ac58e9f
https://github.com/dyninst/dyninst/commit/a5871968d646bb6ac156f03e01f60c363ac58e9f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: b3b30003da35509ad6ea09934dd1745bf7bbea05
https://github.com/dyninst/dyninst/commit/b3b30003da35509ad6ea09934dd1745bf7bbea05
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: 0c32dea4e2a9f698df92d475c70fbcbd432570e4
https://github.com/dyninst/dyninst/commit/0c32dea4e2a9f698df92d475c70fbcbd432570e4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: ee559e4d7ae668b036152b248cb3b381d22bc00c
https://github.com/dyninst/dyninst/commit/ee559e4d7ae668b036152b248cb3b381d22bc00c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: c273b56f0cd1edea3071fe8eaa030f56c5d7f5b7
https://github.com/dyninst/dyninst/commit/c273b56f0cd1edea3071fe8eaa030f56c5d7f5b7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: d5ad72b682d8f0be1b8969dc810270a6ab948b8a
https://github.com/dyninst/dyninst/commit/d5ad72b682d8f0be1b8969dc810270a6ab948b8a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: 50e56ba0b2f53e9bcd0e105344fc2bb57a9c4a72
https://github.com/dyninst/dyninst/commit/50e56ba0b2f53e9bcd0e105344fc2bb57a9c4a72
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: c137ab8e02fd9237c22f7781f9cc487c4a45e7b7
https://github.com/dyninst/dyninst/commit/c137ab8e02fd9237c22f7781f9cc487c4a45e7b7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: 9a2b8a77002dce1aee98e6a18e503cfcd872621d
https://github.com/dyninst/dyninst/commit/9a2b8a77002dce1aee98e6a18e503cfcd872621d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: 7aeb1c5ac52c6ae4d6beae055970d2a0d15f9f15
https://github.com/dyninst/dyninst/commit/7aeb1c5ac52c6ae4d6beae055970d2a0d15f9f15
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: 51242660de882bd7d95f4c55700140d04c5baac7
https://github.com/dyninst/dyninst/commit/51242660de882bd7d95f4c55700140d04c5baac7
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: 658c6d20c661052e89f81a9a18cf54a799cce366
https://github.com/dyninst/dyninst/commit/658c6d20c661052e89f81a9a18cf54a799cce366
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: 8b5d9348c3b375223b12046d50634e63c5c63457
https://github.com/dyninst/dyninst/commit/8b5d9348c3b375223b12046d50634e63c5c63457
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: 63e7e6f79447d2f6e28b0c7f8c27567d345cc9a0
https://github.com/dyninst/dyninst/commit/63e7e6f79447d2f6e28b0c7f8c27567d345cc9a0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: f7fc9a01294923dd72c220b4b57e74062f225c7f
https://github.com/dyninst/dyninst/commit/f7fc9a01294923dd72c220b4b57e74062f225c7f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: 426963e22c88d1f0526779d1838b009161b35f45
https://github.com/dyninst/dyninst/commit/426963e22c88d1f0526779d1838b009161b35f45
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: 59e6d2479eceb0c9a6c9c8b05e3536f6d33710aa
https://github.com/dyninst/dyninst/commit/59e6d2479eceb0c9a6c9c8b05e3536f6d33710aa
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: 0b4cfea60c451ab786bc97eba6651d8c9ae466dc
https://github.com/dyninst/dyninst/commit/0b4cfea60c451ab786bc97eba6651d8c9ae466dc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: e73e3ecc3de1ea575c41d7f9e4403fe081e172bb
https://github.com/dyninst/dyninst/commit/e73e3ecc3de1ea575c41d7f9e4403fe081e172bb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: 77160dbbd82363207b6f75d04ad1ba1f351340f1
https://github.com/dyninst/dyninst/commit/77160dbbd82363207b6f75d04ad1ba1f351340f1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/h/entryIDs.h
A common/src/arch-riscv64.h
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: 51559a0b9abe4147c3a496cbbe5bb026519dcfe4
https://github.com/dyninst/dyninst/commit/51559a0b9abe4147c3a496cbbe5bb026519dcfe4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: fe110a213eed8d35449abd75a6e5934d3620ebea
https://github.com/dyninst/dyninst/commit/fe110a213eed8d35449abd75a6e5934d3620ebea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
Log Message:
-----------
Add RISC-V ParseAPI
Commit: de5f62c19a74d76031d578720b371b9ddf92ae90
https://github.com/dyninst/dyninst/commit/de5f62c19a74d76031d578720b371b9ddf92ae90
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: 4c3c4e5757cba2b020d8b43f0fd8b2f317beb671
https://github.com/dyninst/dyninst/commit/4c3c4e5757cba2b020d8b43f0fd8b2f317beb671
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: a847f39a0bc3db3dfe70423752c3dadb317344b4
https://github.com/dyninst/dyninst/commit/a847f39a0bc3db3dfe70423752c3dadb317344b4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: 896fc706b6af184a1fe7d81715c4105f80a781f0
https://github.com/dyninst/dyninst/commit/896fc706b6af184a1fe7d81715c4105f80a781f0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: 69ca189c8464738b57302fd4e08e8700fbda2aa5
https://github.com/dyninst/dyninst/commit/69ca189c8464738b57302fd4e08e8700fbda2aa5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: cc178c2c130a4a4414d2726e235a9cc9651ac4b0
https://github.com/dyninst/dyninst/commit/cc178c2c130a4a4414d2726e235a9cc9651ac4b0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: 7fb10c04c23387555bc2859119f8700d38168e21
https://github.com/dyninst/dyninst/commit/7fb10c04c23387555bc2859119f8700d38168e21
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: a1c3b59edf070051ffd4151e7ade6dd05f53239d
https://github.com/dyninst/dyninst/commit/a1c3b59edf070051ffd4151e7ade6dd05f53239d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: 73ccee8107c487ec40d7af4d6361fa561cfdc3e9
https://github.com/dyninst/dyninst/commit/73ccee8107c487ec40d7af4d6361fa561cfdc3e9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: 4b809b51f13307af55506e9225ce87dadd96f89d
https://github.com/dyninst/dyninst/commit/4b809b51f13307af55506e9225ce87dadd96f89d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: d694db25fdb11cb4388cddce2aed6c4513a45acb
https://github.com/dyninst/dyninst/commit/d694db25fdb11cb4388cddce2aed6c4513a45acb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
A dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 1bc40607fcd8180493d4b8d921fb80f1ab8b184d
https://github.com/dyninst/dyninst/commit/1bc40607fcd8180493d4b8d921fb80f1ab8b184d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: 42d19ed91796b4cdaf10f937d0b29e720873fa04
https://github.com/dyninst/dyninst/commit/42d19ed91796b4cdaf10f937d0b29e720873fa04
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: 3b77eb3216f2a67eeb7193445ae28220d6d7f144
https://github.com/dyninst/dyninst/commit/3b77eb3216f2a67eeb7193445ae28220d6d7f144
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: 53289f15fff4995e526980cd5b26c5346dd35d3c
https://github.com/dyninst/dyninst/commit/53289f15fff4995e526980cd5b26c5346dd35d3c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: a59bced6e7b3a334c3e5eb5568989579bc7a7d08
https://github.com/dyninst/dyninst/commit/a59bced6e7b3a334c3e5eb5568989579bc7a7d08
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: bcc0e2da3764a8446523b99c04606edb2092de75
https://github.com/dyninst/dyninst/commit/bcc0e2da3764a8446523b99c04606edb2092de75
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: 72b17105cc3d1e75db41c61cf6d631005cb09e92
https://github.com/dyninst/dyninst/commit/72b17105cc3d1e75db41c61cf6d631005cb09e92
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: 956ae44b1af0dc9d773f18b37b11cc38c8acc315
https://github.com/dyninst/dyninst/commit/956ae44b1af0dc9d773f18b37b11cc38c8acc315
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: eff8be33e38fb1670018feba6a958005ddda55d0
https://github.com/dyninst/dyninst/commit/eff8be33e38fb1670018feba6a958005ddda55d0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: 02e5a3295184640d5ce2f7e483d1c248d6749094
https://github.com/dyninst/dyninst/commit/02e5a3295184640d5ce2f7e483d1c248d6749094
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/src/convertOpcodes.C
M dyninstAPI/src/inst-riscv64.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: eab456a5be41a3d8375d9c3b35413c00f79a2afc
https://github.com/dyninst/dyninst/commit/eab456a5be41a3d8375d9c3b35413c00f79a2afc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: 6c5218f441512cee2806cc8ca7efdc7a12518dea
https://github.com/dyninst/dyninst/commit/6c5218f441512cee2806cc8ca7efdc7a12518dea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: 307464bdead826086dbaa087f8578a1ca4cdcec7
https://github.com/dyninst/dyninst/commit/307464bdead826086dbaa087f8578a1ca4cdcec7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: 2b04cb84a46022a58d208f75416735b17cf803c4
https://github.com/dyninst/dyninst/commit/2b04cb84a46022a58d208f75416735b17cf803c4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: 1735c8f8bebb234e15df1b852b1b279878debdc6
https://github.com/dyninst/dyninst/commit/1735c8f8bebb234e15df1b852b1b279878debdc6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: 648a03d1a85065e34ff81acb56f898f11f9a7cac
https://github.com/dyninst/dyninst/commit/648a03d1a85065e34ff81acb56f898f11f9a7cac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: b056625ca8cac92e57e58c774d6a5965adf83c42
https://github.com/dyninst/dyninst/commit/b056625ca8cac92e57e58c774d6a5965adf83c42
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: c2d74ab27f00fd084818afe10d7b7b2dc96b0dae
https://github.com/dyninst/dyninst/commit/c2d74ab27f00fd084818afe10d7b7b2dc96b0dae
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: 6715d624db213475244df6eb338376f240159082
https://github.com/dyninst/dyninst/commit/6715d624db213475244df6eb338376f240159082
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: 44b718b0282803bcd79bb5d60a7253eeaee190b8
https://github.com/dyninst/dyninst/commit/44b718b0282803bcd79bb5d60a7253eeaee190b8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: b79693782d84385461074ef52fc40317a91c4942
https://github.com/dyninst/dyninst/commit/b79693782d84385461074ef52fc40317a91c4942
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: 273edc816a89a0624d2c9fc816763298be5f902c
https://github.com/dyninst/dyninst/commit/273edc816a89a0624d2c9fc816763298be5f902c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: 2818950f4182ca784990228cd2e0c3dd710828e7
https://github.com/dyninst/dyninst/commit/2818950f4182ca784990228cd2e0c3dd710828e7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: a1a8fe34b1207a7f03eb1df7ef296d923e75fa45
https://github.com/dyninst/dyninst/commit/a1a8fe34b1207a7f03eb1df7ef296d923e75fa45
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 0c3d7aed341e30f702640b65a0d87cf3a8f27532
https://github.com/dyninst/dyninst/commit/0c3d7aed341e30f702640b65a0d87cf3a8f27532
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: 7d7c2fd482cd74c043a6c720c70eeb117ff4b5b9
https://github.com/dyninst/dyninst/commit/7d7c2fd482cd74c043a6c720c70eeb117ff4b5b9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: 978d6e559adbf861748daec84e8d9271f1671c6b
https://github.com/dyninst/dyninst/commit/978d6e559adbf861748daec84e8d9271f1671c6b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: 75d0c858f3d676c1b4afeb01a767b0977404ff31
https://github.com/dyninst/dyninst/commit/75d0c858f3d676c1b4afeb01a767b0977404ff31
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: 16cc225248fb35db4f878bc717d792d81d2e1ef9
https://github.com/dyninst/dyninst/commit/16cc225248fb35db4f878bc717d792d81d2e1ef9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: 6c3d6df5eefbbe068830cb779c7b9b8cd1a6953e
https://github.com/dyninst/dyninst/commit/6c3d6df5eefbbe068830cb779c7b9b8cd1a6953e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: 7b1141724fb5eb309989eccbab3a9091c3e5ec08
https://github.com/dyninst/dyninst/commit/7b1141724fb5eb309989eccbab3a9091c3e5ec08
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 4185378b3d4f3529e86e00957fe9e2720da7714e
https://github.com/dyninst/dyninst/commit/4185378b3d4f3529e86e00957fe9e2720da7714e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 5b74a37bf855efbde809624d9f3a0cb1df3f70b9
https://github.com/dyninst/dyninst/commit/5b74a37bf855efbde809624d9f3a0cb1df3f70b9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: 887c90157517230629b7fff5561e72ca3b0c4e9a
https://github.com/dyninst/dyninst/commit/887c90157517230629b7fff5561e72ca3b0c4e9a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: 95eef216fd96bf5ff857b0488b5cfdacf641093e
https://github.com/dyninst/dyninst/commit/95eef216fd96bf5ff857b0488b5cfdacf641093e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: 584f88c543244d918d042703f078215f6bf4f3ee
https://github.com/dyninst/dyninst/commit/584f88c543244d918d042703f078215f6bf4f3ee
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix some bugs
Commit: 5378b3c5a56b160c57086dca6febd9917d44e9db
https://github.com/dyninst/dyninst/commit/5378b3c5a56b160c57086dca6febd9917d44e9db
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: 7ddfe542077a02facfbaa6759c3e04905beebb9e
https://github.com/dyninst/dyninst/commit/7ddfe542077a02facfbaa6759c3e04905beebb9e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: 71f031ac5f2ab3b64d165590c35334b48b720518
https://github.com/dyninst/dyninst/commit/71f031ac5f2ab3b64d165590c35334b48b720518
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: 6f49a2c995ad2a5ba903476e964e50bd4e9e9a7b
https://github.com/dyninst/dyninst/commit/6f49a2c995ad2a5ba903476e964e50bd4e9e9a7b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: 4f7564578fff5b3c71eeb75d5889da22441a4fad
https://github.com/dyninst/dyninst/commit/4f7564578fff5b3c71eeb75d5889da22441a4fad
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: 9316661b45711122694a99cfeb8c9d23d8af7296
https://github.com/dyninst/dyninst/commit/9316661b45711122694a99cfeb8c9d23d8af7296
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: b4744378f2997ca20258b4cd3c02eeff1f189bcd
https://github.com/dyninst/dyninst/commit/b4744378f2997ca20258b4cd3c02eeff1f189bcd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: 9f11d442cbc4cc58990c047565177884d55e1578
https://github.com/dyninst/dyninst/commit/9f11d442cbc4cc58990c047565177884d55e1578
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: cb881c2451ad5252ad007c91206f8f9be90362e4
https://github.com/dyninst/dyninst/commit/cb881c2451ad5252ad007c91206f8f9be90362e4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: 37c46eed315ccd9863a27dadbee760b034655ae8
https://github.com/dyninst/dyninst/commit/37c46eed315ccd9863a27dadbee760b034655ae8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: 6bb143d0245bfdbe2a00f82d20e6c2e375589e2b
https://github.com/dyninst/dyninst/commit/6bb143d0245bfdbe2a00f82d20e6c2e375589e2b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: 108d36b61ba9c51d495ad7d3dd2f072b25a224be
https://github.com/dyninst/dyninst/commit/108d36b61ba9c51d495ad7d3dd2f072b25a224be
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: cf006691a6003cbdfa79c6a7343d7750af62c609
https://github.com/dyninst/dyninst/commit/cf006691a6003cbdfa79c6a7343d7750af62c609
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: 5193ef404ba29274dbdb283ac39d44d922308b96
https://github.com/dyninst/dyninst/commit/5193ef404ba29274dbdb283ac39d44d922308b96
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: 778ecc3ac166259bf5de518c83d7de0490ea447f
https://github.com/dyninst/dyninst/commit/778ecc3ac166259bf5de518c83d7de0490ea447f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: a645180b0af72bf0fab095109e24ae0556dafb68
https://github.com/dyninst/dyninst/commit/a645180b0af72bf0fab095109e24ae0556dafb68
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: c828acd6510f75ab70e2b8feb4bea6225fcc4af1
https://github.com/dyninst/dyninst/commit/c828acd6510f75ab70e2b8feb4bea6225fcc4af1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: a32d5db48cebb4842414231a6cd356a62aa8dc7f
https://github.com/dyninst/dyninst/commit/a32d5db48cebb4842414231a6cd356a62aa8dc7f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: 207fe7c2252e201cf721509c5fb04f4fd96dbf25
https://github.com/dyninst/dyninst/commit/207fe7c2252e201cf721509c5fb04f4fd96dbf25
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: 2c9c0cc5a068707bc9ae4ca91ab0674a90720a68
https://github.com/dyninst/dyninst/commit/2c9c0cc5a068707bc9ae4ca91ab0674a90720a68
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: 83b659c1602ee0016c6fddd9b408e0dd45030662
https://github.com/dyninst/dyninst/commit/83b659c1602ee0016c6fddd9b408e0dd45030662
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: 3230cc5cd2e0a44e9d9908c4b7e3dcb7e813d918
https://github.com/dyninst/dyninst/commit/3230cc5cd2e0a44e9d9908c4b7e3dcb7e813d918
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: 5a6e662b9ad367664fb6ab61095d75d3643b2fe6
https://github.com/dyninst/dyninst/commit/5a6e662b9ad367664fb6ab61095d75d3643b2fe6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: 961b630e98b9281ae92c8d388d36b476e0c5c552
https://github.com/dyninst/dyninst/commit/961b630e98b9281ae92c8d388d36b476e0c5c552
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: 4c827e0e17df78fe161e6a976bf5b2e614c3af10
https://github.com/dyninst/dyninst/commit/4c827e0e17df78fe161e6a976bf5b2e614c3af10
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: 2dedf0babe02d1edbb09ac5e8c944b702f3a2ae2
https://github.com/dyninst/dyninst/commit/2dedf0babe02d1edbb09ac5e8c944b702f3a2ae2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: e8cb4ad69ae8d09275089a5cbac18c0c0d4848e7
https://github.com/dyninst/dyninst/commit/e8cb4ad69ae8d09275089a5cbac18c0c0d4848e7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
Log Message:
-----------
Add flag to compressed instructions generation
Commit: 27f9e23f0e4257aca3b4c38e5c3b9b51672ee600
https://github.com/dyninst/dyninst/commit/27f9e23f0e4257aca3b4c38e5c3b9b51672ee600
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/req.txt
Log Message:
-----------
Huge update
Commit: b65ab0c087219a70ce8076763dec70232cc04b08
https://github.com/dyninst/dyninst/commit/b65ab0c087219a70ce8076763dec70232cc04b08
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Split codegen into multiple of 16 bits
Commit: 92ba6b472a4a5e08815f3166cb681add6dd777f1
https://github.com/dyninst/dyninst/commit/92ba6b472a4a5e08815f3166cb681add6dd777f1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix indexing issue
Commit: 0b47a687b0fbff7c1fdddd6dcd2debb8d83807db
https://github.com/dyninst/dyninst/commit/0b47a687b0fbff7c1fdddd6dcd2debb8d83807db
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix RISC-V ret bugs
Commit: 34d602ac1b3de67e6c2a3534d7ca3b5321090015
https://github.com/dyninst/dyninst/commit/34d602ac1b3de67e6c2a3534d7ca3b5321090015
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Fix stack and instruction bugs
Commit: 43b52286f36801544a1173391800454e8153f56a
https://github.com/dyninst/dyninst/commit/43b52286f36801544a1173391800454e8153f56a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix long branch bug
Commit: b50a5c76b12fc6e214e0d1d2ec69cddbd37ebc3f
https://github.com/dyninst/dyninst/commit/b50a5c76b12fc6e214e0d1d2ec69cddbd37ebc3f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add modifyData and fix auipc jalr bug
Commit: 5cd518402bd4eaa51c759ed1c89376a1b1c2dfbb
https://github.com/dyninst/dyninst/commit/5cd518402bd4eaa51c759ed1c89376a1b1c2dfbb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M proccontrol/src/riscv_process.C
Log Message:
-----------
Add Marco's patch
Commit: ee6809e6172d5fdd8328048b3317cde5026a43db
https://github.com/dyninst/dyninst/commit/ee6809e6172d5fdd8328048b3317cde5026a43db
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Commit: cd54549530199775ad6bf4f6f9d416efe785225a
https://github.com/dyninst/dyninst/commit/cd54549530199775ad6bf4f6f9d416efe785225a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Patch RISC-V SAIL parser
Commit: 67218a6f4ff461a125958a69ec151e9402cfd654
https://github.com/dyninst/dyninst/commit/67218a6f4ff461a125958a69ec151e9402cfd654
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Fix parse_riscv_attribute API
Commit: 8ab1d1b493eed15de9ed7085967fd3b656c67409
https://github.com/dyninst/dyninst/commit/8ab1d1b493eed15de9ed7085967fd3b656c67409
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
M parseAPI/src/IA_riscv64.C
M proccontrol/src/riscv_process.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Fix include arch-riscv64.h
Commit: eed2ff536cd06327fbfd343a9e3fb44959ae18c5
https://github.com/dyninst/dyninst/commit/eed2ff536cd06327fbfd343a9e3fb44959ae18c5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Revert emitElfStatic-riscv64.C
Commit: e8240056f292ac568fd0371b7f943c56bf233884
https://github.com/dyninst/dyninst/commit/e8240056f292ac568fd0371b7f943c56bf233884
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M proccontrol/src/riscv_process.C
Log Message:
-----------
Fix Object ELF
Commit: 52a1e29d7282b48a258c7825c1194d22f4caf1e9
https://github.com/dyninst/dyninst/commit/52a1e29d7282b48a258c7825c1194d22f4caf1e9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Solve RISC-V PLT issue
Commit: 6d7493af2dbce3dc65c71fc93204d4d32678527d
https://github.com/dyninst/dyninst/commit/6d7493af2dbce3dc65c71fc93204d4d32678527d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
64 ->XLENBITS
Commit: 862d7db8627733cb29c28ddff05ef749ef2db8ad
https://github.com/dyninst/dyninst/commit/862d7db8627733cb29c28ddff05ef749ef2db8ad
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite constant constraints
Commit: 997756403b7a52a8619aa60f6e0539d2c3fc6bfc
https://github.com/dyninst/dyninst/commit/997756403b7a52a8619aa60f6e0539d2c3fc6bfc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Implement missing memory codegen and fix wrong emitImm
Commit: 5c6b030920a22fd911485a51ac9607b1680a1f42
https://github.com/dyninst/dyninst/commit/5c6b030920a22fd911485a51ac9607b1680a1f42
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing instructions in instructionAPI
Commit: a28bffd025aa80cefef1756203971dd3db282633
https://github.com/dyninst/dyninst/commit/a28bffd025aa80cefef1756203971dd3db282633
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix c.lui
Commit: af63579e62c21a2a967854ef4cca8284bb84aa61
https://github.com/dyninst/dyninst/commit/af63579e62c21a2a967854ef4cca8284bb84aa61
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Correct storing registers in emitCall
Commit: 9ca325bbef2e8d766e9a1166bf97a0de067e8912
https://github.com/dyninst/dyninst/commit/9ca325bbef2e8d766e9a1166bf97a0de067e8912
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing atomic instruction in InstructionAPI
Commit: cbc47c67b3b0aad077d79b2d1e1cbc2416ea0a07
https://github.com/dyninst/dyninst/commit/cbc47c67b3b0aad077d79b2d1e1cbc2416ea0a07
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix inter modular function address
Commit: 7d7432a9999bbb0c9db75f48d148b27f5230d539
https://github.com/dyninst/dyninst/commit/7d7432a9999bbb0c9db75f48d148b27f5230d539
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Add branch via trap for RISC-V
Commit: 4f5e3e716412e4c6993c338f12e3e78e6fccc6b7
https://github.com/dyninst/dyninst/commit/4f5e3e716412e4c6993c338f12e3e78e6fccc6b7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Pull register space from address space
Commit: 25317ce6a001f121cdda7eb272029e6dde9b7854
https://github.com/dyninst/dyninst/commit/25317ce6a001f121cdda7eb272029e6dde9b7854
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
Log Message:
-----------
Fix wrong ElfX_Dyn
Commit: fe6c829c5032f858f4a0ab86bcb7f0b5d7dd4f35
https://github.com/dyninst/dyninst/commit/fe6c829c5032f858f4a0ab86bcb7f0b5d7dd4f35
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix call instruction codegen bugs
Commit: b1560e290b8df05ebaff0d4ff6643fa788370be1
https://github.com/dyninst/dyninst/commit/b1560e290b8df05ebaff0d4ff6643fa788370be1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix lui signedness problem
Commit: 9303c050d7efb40ee5bcf56e6e234db6a294c8bd
https://github.com/dyninst/dyninst/commit/9303c050d7efb40ee5bcf56e6e234db6a294c8bd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Minor adjustment in RISCV emitElfStatic
Commit: c407468061cf4ec765c806d69dbc4d43eb04c0bb
https://github.com/dyninst/dyninst/commit/c407468061cf4ec765c806d69dbc4d43eb04c0bb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add missing addressWidth
Commit: 2df3affa9608a58e8c64e37fdcce9c68f0a559e3
https://github.com/dyninst/dyninst/commit/2df3affa9608a58e8c64e37fdcce9c68f0a559e3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen.C
Log Message:
-----------
Variable length buffer
Commit: 54b38227604c0f0342677b72a14b1a0230715dac
https://github.com/dyninst/dyninst/commit/54b38227604c0f0342677b72a14b1a0230715dac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix incorrect offset in emitCall and emitLoadShared
Commit: 5115553e800a0f339c2de9f41b0c732177b1c943
https://github.com/dyninst/dyninst/commit/5115553e800a0f339c2de9f41b0c732177b1c943
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
beq to bne
Commit: 39279638ffaa3a80cc201ec3d0fbb3f1ab91110c
https://github.com/dyninst/dyninst/commit/39279638ffaa3a80cc201ec3d0fbb3f1ab91110c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M instructionAPI/src/InstructionDecoder-Capstone.C
Log Message:
-----------
Fix indentation
Commit: 986404a68e7a766d710960c5d84b1b17708eadd3
https://github.com/dyninst/dyninst/commit/986404a68e7a766d710960c5d84b1b17708eadd3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Improve immediate calculation algorithm
Commit: 5459d3d86da580ec63941b7d5efb6ca85b7ec873
https://github.com/dyninst/dyninst/commit/5459d3d86da580ec63941b7d5efb6ca85b7ec873
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Remove optimization for relative load store
Commit: d43f7cfb9cea7032635a3cf0f4d1597830c1a3a1
https://github.com/dyninst/dyninst/commit/d43f7cfb9cea7032635a3cf0f4d1597830c1a3a1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix conditional branch offset error
Commit: 4296d473f1562cd1390e363d6e5b00c7d3acada6
https://github.com/dyninst/dyninst/commit/4296d473f1562cd1390e363d6e5b00c7d3acada6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix jump offset
Commit: b67a2647dfc1384bbeb682fccd6cd40ee9997ba8
https://github.com/dyninst/dyninst/commit/b67a2647dfc1384bbeb682fccd6cd40ee9997ba8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Fix jump target in emitIf
Commit: c8da277cbb0a0f9fe60692f3e6d1b69591aa41a2
https://github.com/dyninst/dyninst/commit/c8da277cbb0a0f9fe60692f3e6d1b69591aa41a2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Tail Call
Commit: f96d84ffa1acc5790a116ac493cc25c0f95dc1ea
https://github.com/dyninst/dyninst/commit/f96d84ffa1acc5790a116ac493cc25c0f95dc1ea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
A dataflowAPI/sail/experimental/sail_semantics.json
A dataflowAPI/sail/experimental/sail_to_rose.pl
Log Message:
-----------
Add Experimental SAIL parser
Commit: d19829105276b3248811eb6a7c26fa9b3af0f907
https://github.com/dyninst/dyninst/commit/d19829105276b3248811eb6a7c26fa9b3af0f907
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
Log Message:
-----------
Support DYNINST_CODEGEN_ARCH_RISCV64
Commit: 6b1df6c86ee6b1550624879a7eabe88f5b992cbf
https://github.com/dyninst/dyninst/commit/6b1df6c86ee6b1550624879a7eabe88f5b992cbf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI_RT/src/RTlinux.c
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add missing CODEGEN
Commit: 8c4cf57edb9ee8c252960a425809f5763d41b424
https://github.com/dyninst/dyninst/commit/8c4cf57edb9ee8c252960a425809f5763d41b424
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/unix.C
Log Message:
-----------
Disallow generating _init and _fini
Commit: 26e908bdb6c4eb526a0978207c8bae9639923537
https://github.com/dyninst/dyninst/commit/26e908bdb6c4eb526a0978207c8bae9639923537
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Add c.ebreak
Commit: 6041335df90a18ec283277794b13ea082e07d02c
https://github.com/dyninst/dyninst/commit/6041335df90a18ec283277794b13ea082e07d02c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
Log Message:
-----------
Remove annonying tab from github workflow
Commit: 484791ce3fb34b394012194c7db4107d485692fc
https://github.com/dyninst/dyninst/commit/484791ce3fb34b394012194c7db4107d485692fc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/Object.C
M symtabAPI/src/Object.h
Log Message:
-----------
Add MAFD extension detection
Commit: 5d4ca8f720df449255d4b82ddde706027a05c5f2
https://github.com/dyninst/dyninst/commit/5d4ca8f720df449255d4b82ddde706027a05c5f2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/AbslocInterface.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Add special handling for convert
Commit: b010f0ad6ee9d299f60ffb6b2a4840278bf0bb9f
https://github.com/dyninst/dyninst/commit/b010f0ad6ee9d299f60ffb6b2a4840278bf0bb9f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dyninstAPI/src/Relocation/Springboard.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/addressSpace.C
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
Log Message:
-----------
Use compressed instruction info
Commit: 336e9be3d9875536bd76b01c7ce1a5d70e75bf2d
https://github.com/dyninst/dyninst/commit/336e9be3d9875536bd76b01c7ce1a5d70e75bf2d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
Log Message:
-----------
Add basic RISC-V pattern matching in ParseAPI, for efficiency
Commit: ab6b1450e4362a2c60c45ac2dfb257b3dbcaf025
https://github.com/dyninst/dyninst/commit/ab6b1450e4362a2c60c45ac2dfb257b3dbcaf025
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/Operation.C
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_aarch64.C
M parseAPI/src/IA_aarch64.h
M parseAPI/src/IA_amdgpu.C
M parseAPI/src/IA_amdgpu.h
M parseAPI/src/IA_power.C
M parseAPI/src/IA_power.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/IA_riscv64.h
M parseAPI/src/IA_x86.C
M parseAPI/src/IA_x86.h
Log Message:
-----------
Move multi instruction jump to separate function
Commit: 09a6482dd6861e038112e67980497d87edfaf0a5
https://github.com/dyninst/dyninst/commit/09a6482dd6861e038112e67980497d87edfaf0a5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/BPatch_object.C
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/binaryEdit.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/h/dyninstAPI_RT.h
M dyninstAPI_RT/src/RTfreebsd.c
M dyninstAPI_RT/src/RTlinux.c
M parseAPI/h/CodeSource.h
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/h/Region.h
M symtabAPI/h/Symtab.h
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Region.C
M symtabAPI/src/Symtab.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Experimental: use .init_array instead of _init
Commit: 116294b1a579dc8cbd0e79602b78b302cd3bd111
https://github.com/dyninst/dyninst/commit/116294b1a579dc8cbd0e79602b78b302cd3bd111
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/BPatch_object.C
M symtabAPI/h/Symtab.h
M symtabAPI/src/Symtab.C
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElf.h
Log Message:
-----------
Make .init_array works
Commit: b9ec8e91c63ace7f1191413e42ab674bebc5f625
https://github.com/dyninst/dyninst/commit/b9ec8e91c63ace7f1191413e42ab674bebc5f625
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/h/BPatch_object.h
M dyninstAPI/src/BPatch_object.C
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/binaryEdit.h
M dyninstAPI/src/unix.C
M symtabAPI/h/Region.h
M symtabAPI/h/Symtab.h
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Region.C
M symtabAPI/src/Symtab.C
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElf.h
Log Message:
-----------
Add .fini_array
Commit: 20f9d7a003db2235beac3979d3bc7dda6be71e49
https://github.com/dyninst/dyninst/commit/20f9d7a003db2235beac3979d3bc7dda6be71e49
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M parseAPI/h/CodeSource.h
M symtabAPI/src/emitElf.C
Log Message:
-----------
Remove warnings
Commit: f5144867f7807c4e3892aec2868501e0194258d7
https://github.com/dyninst/dyninst/commit/f5144867f7807c4e3892aec2868501e0194258d7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/h/BPatch_object.h
M dyninstAPI/src/BPatch_object.C
Log Message:
-----------
Instrument _init and _fini if exists
Commit: 0946f3d881a8503adb5a9711e35c693e3f5870cc
https://github.com/dyninst/dyninst/commit/0946f3d881a8503adb5a9711e35c693e3f5870cc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/binaryEdit.h
M dyninstAPI/src/unix.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Create _dyninstInit and _dyninstFini if exists
Commit: ae0b8dcf7292bae3dc2622cca2ae38e1208005c0
https://github.com/dyninst/dyninst/commit/ae0b8dcf7292bae3dc2622cca2ae38e1208005c0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
A dyninstAPI/src/dynProcess-riscv64.C
M dyninstAPI/src/function.h
M dyninstAPI/src/inst-riscv64.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Add dynProcess
Commit: a815851dc3f4a9aec5ab7dfd6ebdf239b48b5797
https://github.com/dyninst/dyninst/commit/a815851dc3f4a9aec5ab7dfd6ebdf239b48b5797
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Make PC read/write explicit
Commit: 7cd2fb2738e7de09a435b575ec2672739e6c2874
https://github.com/dyninst/dyninst/commit/7cd2fb2738e7de09a435b575ec2672739e6c2874
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix implicit register PC
Commit: cd06a0addb7c4f78dc2390b7fe8d5546dba4ddd1
https://github.com/dyninst/dyninst/commit/cd06a0addb7c4f78dc2390b7fe8d5546dba4ddd1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/AbslocInterface.C
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Remove implicit registers from compressed jump instructions
Commit: fadea6aa5fe0419c2a07cadeeb8dc47ff78d0325
https://github.com/dyninst/dyninst/commit/fadea6aa5fe0419c2a07cadeeb8dc47ff78d0325
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/AbslocInterface.C
Log Message:
-----------
Add explicit conditional branch instruction assignments
Commit: 3f87261559d1f15dd55ae39906dce6538eb01307
https://github.com/dyninst/dyninst/commit/3f87261559d1f15dd55ae39906dce6538eb01307
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/src/BoundFactData.C
Log Message:
-----------
Add explicit conditional bound for RISC-V branch instructions
Commit: 5810a9dc3a71df13c9f1f32389d9dc15f5925f50
https://github.com/dyninst/dyninst/commit/5810a9dc3a71df13c9f1f32389d9dc15f5925f50
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.C
Log Message:
-----------
Optimize spilled registers
Commit: 17a03d43acad718ab75b85bfe6822ff9daed3078
https://github.com/dyninst/dyninst/commit/17a03d43acad718ab75b85bfe6822ff9daed3078
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
Log Message:
-----------
Add constants for compressed load/store
Commit: 28d8e385471fa958a636fbda1af260130afcd470
https://github.com/dyninst/dyninst/commit/28d8e385471fa958a636fbda1af260130afcd470
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Refactor RISC-V Codegen
Commit: 09ab825cc0a62cdc229a0918d9f9ef084ac7a1ec
https://github.com/dyninst/dyninst/commit/09ab825cc0a62cdc229a0918d9f9ef084ac7a1ec
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Set gp and tp as callee saved registers
Commit: b84593e73a51625847390d963ee2e2dc6427decf
https://github.com/dyninst/dyninst/commit/b84593e73a51625847390d963ee2e2dc6427decf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Minimize stack spill space
Commit: 12bc95f34e5df27b4857fed80b93d72383176fcf
https://github.com/dyninst/dyninst/commit/12bc95f34e5df27b4857fed80b93d72383176fcf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/h/Operation_impl.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_aarch64.C
M parseAPI/src/IA_aarch64.h
M parseAPI/src/IA_amdgpu.C
M parseAPI/src/IA_amdgpu.h
M parseAPI/src/IA_power.C
M parseAPI/src/IA_power.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/IA_riscv64.h
M parseAPI/src/IA_x86.C
M parseAPI/src/IA_x86.h
Log Message:
-----------
Use pointer instead of reference for target address calculation
Commit: caca8673ca11c216b986b13bbf422eed7f4d3e43
https://github.com/dyninst/dyninst/commit/caca8673ca11c216b986b13bbf422eed7f4d3e43
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix stack spill height
Commit: ca6f6c2db6d23e3b07a203ea18df914a516b547d
https://github.com/dyninst/dyninst/commit/ca6f6c2db6d23e3b07a203ea18df914a516b547d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
Log Message:
-----------
Migrate .rela.dyn to general isMultiInsnJump
Commit: d8286e1abdaaeec8c6dcfebc77d19442d358a18b
https://github.com/dyninst/dyninst/commit/d8286e1abdaaeec8c6dcfebc77d19442d358a18b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Move check jump range out from isMultiInsnJump
Commit: b198c3c77ae125e34df0be4150223b9061a0c7cc
https://github.com/dyninst/dyninst/commit/b198c3c77ae125e34df0be4150223b9061a0c7cc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M parseAPI/src/BoundFactCalculator.C
M parseAPI/src/BoundFactData.C
M parseAPI/src/IndirectAnalyzer.C
Log Message:
-----------
Fix RISC-V jump table incorrect bound
Commit: 0680c380fffcf05d6afc857483282476dddb69a7
https://github.com/dyninst/dyninst/commit/0680c380fffcf05d6afc857483282476dddb69a7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M common/h/entryIDs.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/Instruction.C
Log Message:
-----------
Fix rebased duplicates
Commit: 1f92db833a3d1a4bf8e77e5214d9c1e51df402d4
https://github.com/dyninst/dyninst/commit/1f92db833a3d1a4bf8e77e5214d9c1e51df402d4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-10-05 (Sun, 05 Oct 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add floating point pseudo instruction
Compare: https://github.com/dyninst/dyninst/compare/d258998b3d7d...1f92db833a3d
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