[DynInst_API:] [dyninst/dyninst] a315b6: Make PC read/write explicit

[wxrdnx <noreply@xxxxxxxxxx>]

  Branch: refs/heads/angushe/riscv
  Home:   https://github.com/dyninst/dyninst
  Commit: a315b6d105285e0e7bfd8b8b68a3021a68816af9
      https://github.com/dyninst/dyninst/commit/a315b6d105285e0e7bfd8b8b68a3021a68816af9
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-09-05 (Fri, 05 Sep 2025)

  Changed paths:
    M instructionAPI/src/InstructionDecoder-riscv64.C

  Log Message:
  -----------
  Make PC read/write explicit


  Commit: 1aa5d73c5eb8393da7ed6373357eb646f84df707
      https://github.com/dyninst/dyninst/commit/1aa5d73c5eb8393da7ed6373357eb646f84df707
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-09-06 (Sat, 06 Sep 2025)

  Changed paths:
    M instructionAPI/src/InstructionDecoder-riscv64.C

  Log Message:
  -----------
  Fix implicit register PC


  Commit: 09f14a549faaa96972a5da79ae4cd4f9e6f7444d
      https://github.com/dyninst/dyninst/commit/09f14a549faaa96972a5da79ae4cd4f9e6f7444d
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-09-06 (Sat, 06 Sep 2025)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherRiscv64.C
    M dataflowAPI/src/AbslocInterface.C
    M dataflowAPI/src/RoseInsnFactory.C
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/InstructionDecoder-riscv64.C
    M parseAPI/src/IA_IAPI.C
    M parseAPI/src/IA_riscv64.C

  Log Message:
  -----------
  Remove implicit registers from compressed jump instructions


  Commit: ddeeea6f91c65b38fa29bac56706f69f76b91c89
      https://github.com/dyninst/dyninst/commit/ddeeea6f91c65b38fa29bac56706f69f76b91c89
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-09-08 (Mon, 08 Sep 2025)

  Changed paths:
    M dataflowAPI/src/AbslocInterface.C

  Log Message:
  -----------
  Add explicit conditional branch instruction assignments


  Commit: 32a0693f7137978b9b557623f6617ba3bff32013
      https://github.com/dyninst/dyninst/commit/32a0693f7137978b9b557623f6617ba3bff32013
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-09-08 (Mon, 08 Sep 2025)

  Changed paths:
    M parseAPI/src/BoundFactData.C

  Log Message:
  -----------
  Add explicit conditional bound for RISC-V branch instructions


Compare: https://github.com/dyninst/dyninst/compare/6a410babc364...32a0693f7137

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