Branch: refs/heads/angushe/experimental-riscv-codegen-arch
Home: https://github.com/dyninst/dyninst
Commit: a962a0615e96524651df74edf0cbd60fc2b72049
https://github.com/dyninst/dyninst/commit/a962a0615e96524651df74edf0cbd60fc2b72049
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: bf2ac47036042690f373c8f90e8b9452968b2279
https://github.com/dyninst/dyninst/commit/bf2ac47036042690f373c8f90e8b9452968b2279
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: 90b79ed9b53daac1b1c8e5f777375da879bb4ed8
https://github.com/dyninst/dyninst/commit/90b79ed9b53daac1b1c8e5f777375da879bb4ed8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: a2f38cd1f002305dd1eaba08d43e0ad80501b0b4
https://github.com/dyninst/dyninst/commit/a2f38cd1f002305dd1eaba08d43e0ad80501b0b4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: 9b83b4a5dd7cbbe4d214a8fcdab816eb2754b1e1
https://github.com/dyninst/dyninst/commit/9b83b4a5dd7cbbe4d214a8fcdab816eb2754b1e1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: f0d472289e8343700ac84d50c84a14f65c85f136
https://github.com/dyninst/dyninst/commit/f0d472289e8343700ac84d50c84a14f65c85f136
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: b8427d27ba87fce32997e37e93c02fb2b79dfd4f
https://github.com/dyninst/dyninst/commit/b8427d27ba87fce32997e37e93c02fb2b79dfd4f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 60498186798032ba25ddb856a57e10f479501cc3
https://github.com/dyninst/dyninst/commit/60498186798032ba25ddb856a57e10f479501cc3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: 7a95c07b11cb3a6d19916e528ad373a1b2df582e
https://github.com/dyninst/dyninst/commit/7a95c07b11cb3a6d19916e528ad373a1b2df582e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: d0da7d0ceafcf954c40e1d716e94cd2763ca1802
https://github.com/dyninst/dyninst/commit/d0da7d0ceafcf954c40e1d716e94cd2763ca1802
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: e9d88e2a1d0492bab9b3bc71d293cdd6019da1b3
https://github.com/dyninst/dyninst/commit/e9d88e2a1d0492bab9b3bc71d293cdd6019da1b3
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 8c78160700d8e5ba08c722072e3936b673f4bfef
https://github.com/dyninst/dyninst/commit/8c78160700d8e5ba08c722072e3936b673f4bfef
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: 0b123d9d0526b00a08bdf460323e47bc3cbcb527
https://github.com/dyninst/dyninst/commit/0b123d9d0526b00a08bdf460323e47bc3cbcb527
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: ebc0ed70c56d6e83ad754b87900eb9bd203810cc
https://github.com/dyninst/dyninst/commit/ebc0ed70c56d6e83ad754b87900eb9bd203810cc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: 0e6684103ce73b71df29e327bf4220f368060b7c
https://github.com/dyninst/dyninst/commit/0e6684103ce73b71df29e327bf4220f368060b7c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: b9412f0b1d153de7131f23fcbb94cca06a81aab4
https://github.com/dyninst/dyninst/commit/b9412f0b1d153de7131f23fcbb94cca06a81aab4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: ed3ac3140ca158dfaf49057bb05dc4813732e150
https://github.com/dyninst/dyninst/commit/ed3ac3140ca158dfaf49057bb05dc4813732e150
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: 83e9c41cff78c14cb3d65f555e502d151acddb08
https://github.com/dyninst/dyninst/commit/83e9c41cff78c14cb3d65f555e502d151acddb08
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: 4b7414fea10d91b68832549201c9b04414602e94
https://github.com/dyninst/dyninst/commit/4b7414fea10d91b68832549201c9b04414602e94
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: 40fb557a9013cc60d5f4d17ca01e009770d5b0e1
https://github.com/dyninst/dyninst/commit/40fb557a9013cc60d5f4d17ca01e009770d5b0e1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: 654ad4e327ed8a9002a8b0f3308f1d5785d878bc
https://github.com/dyninst/dyninst/commit/654ad4e327ed8a9002a8b0f3308f1d5785d878bc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: bc4beff723c27423a59700574cd12111fcced8fb
https://github.com/dyninst/dyninst/commit/bc4beff723c27423a59700574cd12111fcced8fb
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: 992be671bfa442a018aa3be5d0a30fbe8dca8ea8
https://github.com/dyninst/dyninst/commit/992be671bfa442a018aa3be5d0a30fbe8dca8ea8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: 3ae8cf8d4fb4da54139f9ad971fd5810e6cd8734
https://github.com/dyninst/dyninst/commit/3ae8cf8d4fb4da54139f9ad971fd5810e6cd8734
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: 17358f8b131e8c318f9f29b164fe2191bb78bb76
https://github.com/dyninst/dyninst/commit/17358f8b131e8c318f9f29b164fe2191bb78bb76
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: 8d891b766c1d715f88b2746fa2460283a581dda5
https://github.com/dyninst/dyninst/commit/8d891b766c1d715f88b2746fa2460283a581dda5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: 7b7756f012f8d89e9c923c67a5212f37a60a2ea2
https://github.com/dyninst/dyninst/commit/7b7756f012f8d89e9c923c67a5212f37a60a2ea2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: 66369b84f6ae14ab31557413951c22341344181e
https://github.com/dyninst/dyninst/commit/66369b84f6ae14ab31557413951c22341344181e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: 2aaa2e9f3d587ba40615b2083e071abf55497630
https://github.com/dyninst/dyninst/commit/2aaa2e9f3d587ba40615b2083e071abf55497630
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: f16fb61989155478cd1af09fb3bebfa50e41fa3f
https://github.com/dyninst/dyninst/commit/f16fb61989155478cd1af09fb3bebfa50e41fa3f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: 4d7a205c5c7858ad117bc9c9025bed92e5af482b
https://github.com/dyninst/dyninst/commit/4d7a205c5c7858ad117bc9c9025bed92e5af482b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: 5d72cef310db46f2a0a20668990e0bba42b3f838
https://github.com/dyninst/dyninst/commit/5d72cef310db46f2a0a20668990e0bba42b3f838
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: d5e40cc82437b40a52bef2cc5645e81d7d989fd0
https://github.com/dyninst/dyninst/commit/d5e40cc82437b40a52bef2cc5645e81d7d989fd0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: f6bc37301945a609379f9c6a7e8801b62ea2e74a
https://github.com/dyninst/dyninst/commit/f6bc37301945a609379f9c6a7e8801b62ea2e74a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: 76ca87acf3b2c940fb9a10bd4069269614aa9449
https://github.com/dyninst/dyninst/commit/76ca87acf3b2c940fb9a10bd4069269614aa9449
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: dabba6aa57d9f2bba4be8d65f404b95d4de8f846
https://github.com/dyninst/dyninst/commit/dabba6aa57d9f2bba4be8d65f404b95d4de8f846
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: 218c3f9dc926f1c8e38e4ab6ac49ec3ac3efde4a
https://github.com/dyninst/dyninst/commit/218c3f9dc926f1c8e38e4ab6ac49ec3ac3efde4a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: 73d93ed9eaaffea54c5d6e158a703439544f6be2
https://github.com/dyninst/dyninst/commit/73d93ed9eaaffea54c5d6e158a703439544f6be2
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: 8b5ba96edabe3bc8f7f6590560ca24b658f9804a
https://github.com/dyninst/dyninst/commit/8b5ba96edabe3bc8f7f6590560ca24b658f9804a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: d9e858da0c62918d44c796f57b57e5101cc05d9c
https://github.com/dyninst/dyninst/commit/d9e858da0c62918d44c796f57b57e5101cc05d9c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: 8e9fc154c3426eba779a0871292fbda41dc8b173
https://github.com/dyninst/dyninst/commit/8e9fc154c3426eba779a0871292fbda41dc8b173
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: 691199a5f8c1cbaea7a4cf97117363ce34bcf8a5
https://github.com/dyninst/dyninst/commit/691199a5f8c1cbaea7a4cf97117363ce34bcf8a5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: c22b2dd440489f61fdeba97ed356c7a11daf918b
https://github.com/dyninst/dyninst/commit/c22b2dd440489f61fdeba97ed356c7a11daf918b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: 81314d01befb468d3da122df1598f0352de613e6
https://github.com/dyninst/dyninst/commit/81314d01befb468d3da122df1598f0352de613e6
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: d9edb30bb18dceeb6e799be78292e57d73b42f05
https://github.com/dyninst/dyninst/commit/d9edb30bb18dceeb6e799be78292e57d73b42f05
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: 4c0a3648ce4a934b3a786533fbf490eab6a4f3f8
https://github.com/dyninst/dyninst/commit/4c0a3648ce4a934b3a786533fbf490eab6a4f3f8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: a7cd6da1815d7c71da5ec8bc8f42f11609a0dd16
https://github.com/dyninst/dyninst/commit/a7cd6da1815d7c71da5ec8bc8f42f11609a0dd16
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: f0a15b56521f9ef8cd5b88bcd1a9aaa77e84ca5d
https://github.com/dyninst/dyninst/commit/f0a15b56521f9ef8cd5b88bcd1a9aaa77e84ca5d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: e0f142e424adb98df2f55282a9fccd074a86f322
https://github.com/dyninst/dyninst/commit/e0f142e424adb98df2f55282a9fccd074a86f322
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/h/Architecture.h
M dwarf/src/dwarfHandle.C
Log Message:
-----------
Add riscv architecture
Commit: fca5797127de8a4eefc90e6b2356a59d557cdced
https://github.com/dyninst/dyninst/commit/fca5797127de8a4eefc90e6b2356a59d557cdced
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: 7040b67b78953608adb7dc83a196a461fb435260
https://github.com/dyninst/dyninst/commit/7040b67b78953608adb7dc83a196a461fb435260
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
A common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: 58876a654b718f42afbbf8a47e9a4ea9ec5b7dac
https://github.com/dyninst/dyninst/commit/58876a654b718f42afbbf8a47e9a4ea9ec5b7dac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M elf/src/Elf_X.C
M proccontrol/src/process.C
Log Message:
-----------
Add cases for Arch_riscv64 to suppress compiler warnings
Commit: 18e605c1d132871c319bc811a75bde49eee75949
https://github.com/dyninst/dyninst/commit/18e605c1d132871c319bc811a75bde49eee75949
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: 5fad275144d63973295c8a488a9b288e784bb428
https://github.com/dyninst/dyninst/commit/5fad275144d63973295c8a488a9b288e784bb428
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
M parseAPI/src/SymbolicExpression.C
Log Message:
-----------
Add RISC-V ParseAPI
Commit: f33755d6cc2a9dcfb9e3414c90321e2408a6d0e5
https://github.com/dyninst/dyninst/commit/f33755d6cc2a9dcfb9e3414c90321e2408a6d0e5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
A external/rose/riscv64InstructionEnum.h
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: a58b76e65254a4bc618d3de0afd07151734a8f13
https://github.com/dyninst/dyninst/commit/a58b76e65254a4bc618d3de0afd07151734a8f13
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: 0618b71b783c91c9d1de039750bc24f579f067d7
https://github.com/dyninst/dyninst/commit/0618b71b783c91c9d1de039750bc24f579f067d7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: 289ead57c60f11e44d8e4ec8f62fdfbe5a7c14e8
https://github.com/dyninst/dyninst/commit/289ead57c60f11e44d8e4ec8f62fdfbe5a7c14e8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: 2efc6f4286947974bfe4c712bfbc7aaaec93bece
https://github.com/dyninst/dyninst/commit/2efc6f4286947974bfe4c712bfbc7aaaec93bece
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: 1a7e39907671825c68db7aa935d2a457be9381a8
https://github.com/dyninst/dyninst/commit/1a7e39907671825c68db7aa935d2a457be9381a8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: d48c4ff917196354bd5ef66975bb879668196284
https://github.com/dyninst/dyninst/commit/d48c4ff917196354bd5ef66975bb879668196284
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/h/Architecture.h
Log Message:
-----------
Add missing riscv64 address width
Commit: bea1bf416718276649f495155b06872b45297105
https://github.com/dyninst/dyninst/commit/bea1bf416718276649f495155b06872b45297105
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: 09f98ecc3cb6c30e5dbf9b8837e2cd6f59d0c4ea
https://github.com/dyninst/dyninst/commit/09f98ecc3cb6c30e5dbf9b8837e2cd6f59d0c4ea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: a1a19d3bfc2dd0da7f196db4b8b3d4f547e57986
https://github.com/dyninst/dyninst/commit/a1a19d3bfc2dd0da7f196db4b8b3d4f547e57986
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: 81fa5fbb85a0aab09bbca0c7a6ec9e3670b53902
https://github.com/dyninst/dyninst/commit/81fa5fbb85a0aab09bbca0c7a6ec9e3670b53902
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: 0ada5e1208287975ef031d8eb8f70e4c72b885de
https://github.com/dyninst/dyninst/commit/0ada5e1208287975ef031d8eb8f70e4c72b885de
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 4a7efd1cb2dcb0d4cef4fd988e46e2257ccb18e0
https://github.com/dyninst/dyninst/commit/4a7efd1cb2dcb0d4cef4fd988e46e2257ccb18e0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: c050505636caa7d35fbb006ac6580acdacb7c5ef
https://github.com/dyninst/dyninst/commit/c050505636caa7d35fbb006ac6580acdacb7c5ef
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: e9c91462ed669aa7a12f53a666754eddfdd7f549
https://github.com/dyninst/dyninst/commit/e9c91462ed669aa7a12f53a666754eddfdd7f549
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: 97b962ddc148cdb01472adc1f715866e9c85b8b0
https://github.com/dyninst/dyninst/commit/97b962ddc148cdb01472adc1f715866e9c85b8b0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: 1c8bd20b058054c93427b1ff9b26c2381f8f2331
https://github.com/dyninst/dyninst/commit/1c8bd20b058054c93427b1ff9b26c2381f8f2331
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/src/emitElfStatic-stub.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: 572e2b4249305be205081cd287d1ee84a6386dc5
https://github.com/dyninst/dyninst/commit/572e2b4249305be205081cd287d1ee84a6386dc5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: be7611d9dfe264794b5b23d7cec2a2d511ab0d53
https://github.com/dyninst/dyninst/commit/be7611d9dfe264794b5b23d7cec2a2d511ab0d53
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
M external/rose/riscv64InstructionEnum.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: d2e6945e7e948334b54672bcd458dd4411511004
https://github.com/dyninst/dyninst/commit/d2e6945e7e948334b54672bcd458dd4411511004
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: a2f344a0d181aaf156c4b7024c9efaa78d44a333
https://github.com/dyninst/dyninst/commit/a2f344a0d181aaf156c4b7024c9efaa78d44a333
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: eb508fc47d1bffab28390d4b1fe2cd889807f999
https://github.com/dyninst/dyninst/commit/eb508fc47d1bffab28390d4b1fe2cd889807f999
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
A dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/convertOpcodes.C
M dwarf/CMakeLists.txt
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M dyninstAPI/src/inst-riscv64.h
M external/rose/riscv64InstructionEnum.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: 89196a218b2f8075366d896a73e2caa5cfe9f65f
https://github.com/dyninst/dyninst/commit/89196a218b2f8075366d896a73e2caa5cfe9f65f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: 700ddf67b3bee96ae0911da4186a381e05035751
https://github.com/dyninst/dyninst/commit/700ddf67b3bee96ae0911da4186a381e05035751
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: 550d919625dc330bdda5cf912902d00d9b4f5cdd
https://github.com/dyninst/dyninst/commit/550d919625dc330bdda5cf912902d00d9b4f5cdd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: 80fa5164b030cc9c5d2e34991d5cf30edc823ba6
https://github.com/dyninst/dyninst/commit/80fa5164b030cc9c5d2e34991d5cf30edc823ba6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: 2d070d63c77206147df02a8c579ccd6d81e91fd0
https://github.com/dyninst/dyninst/commit/2d070d63c77206147df02a8c579ccd6d81e91fd0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: e23c036213a7df81466ba2cdf4e013fac39e4f85
https://github.com/dyninst/dyninst/commit/e23c036213a7df81466ba2cdf4e013fac39e4f85
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: 1b8d8ff9da57624ffcb884466dbacec522eece8c
https://github.com/dyninst/dyninst/commit/1b8d8ff9da57624ffcb884466dbacec522eece8c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: 0d5b948ff00534589ea5468c194b84e79840a58b
https://github.com/dyninst/dyninst/commit/0d5b948ff00534589ea5468c194b84e79840a58b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: 504974d10443a5e961c4a57c42b47e69a97bbcd5
https://github.com/dyninst/dyninst/commit/504974d10443a5e961c4a57c42b47e69a97bbcd5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: add428d40ec62d4ba1d1aaeaa11ae3a4c89d9dfe
https://github.com/dyninst/dyninst/commit/add428d40ec62d4ba1d1aaeaa11ae3a4c89d9dfe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: 71bf41e953a5b7f6dceacc25f04c9cb600ec5075
https://github.com/dyninst/dyninst/commit/71bf41e953a5b7f6dceacc25f04c9cb600ec5075
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: 63cd15a590a38be7538fbe20af7ce95cccc6ff37
https://github.com/dyninst/dyninst/commit/63cd15a590a38be7538fbe20af7ce95cccc6ff37
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: 02b4bdbfbd5aa5945ac32bfc3d87a696c35d42ea
https://github.com/dyninst/dyninst/commit/02b4bdbfbd5aa5945ac32bfc3d87a696c35d42ea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: ae04b88a13f387b7dc788b82acba57c957f523d3
https://github.com/dyninst/dyninst/commit/ae04b88a13f387b7dc788b82acba57c957f523d3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 050950d87d7b18b9cde7597bdc30d8411974d37e
https://github.com/dyninst/dyninst/commit/050950d87d7b18b9cde7597bdc30d8411974d37e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: e35726dd0067879549e55ba14eaf91d9869a1bef
https://github.com/dyninst/dyninst/commit/e35726dd0067879549e55ba14eaf91d9869a1bef
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: 75fedf2ca851f2bf8cd2e9751928c742e104fe31
https://github.com/dyninst/dyninst/commit/75fedf2ca851f2bf8cd2e9751928c742e104fe31
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: 7b5cf4179d8ef7389b97a57aaf0bd45cdda47a9e
https://github.com/dyninst/dyninst/commit/7b5cf4179d8ef7389b97a57aaf0bd45cdda47a9e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: 39cd89186932fd467fd8a9641cedc9f13fc03c52
https://github.com/dyninst/dyninst/commit/39cd89186932fd467fd8a9641cedc9f13fc03c52
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: 0cde96c6e1e3f2aeaba70f53a991247c97c9829e
https://github.com/dyninst/dyninst/commit/0cde96c6e1e3f2aeaba70f53a991247c97c9829e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/rose/registers/riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: 73c6e823dd7562c37184c2a62943b64cb0154e4d
https://github.com/dyninst/dyninst/commit/73c6e823dd7562c37184c2a62943b64cb0154e4d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 921bf499916a062682735eb1ec4b2c179204a5b1
https://github.com/dyninst/dyninst/commit/921bf499916a062682735eb1ec4b2c179204a5b1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 00bf69c29df0e339c399cc02d53868fb05e98d36
https://github.com/dyninst/dyninst/commit/00bf69c29df0e339c399cc02d53868fb05e98d36
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: 90cbd22e36a84ca88c242d047ea7bee8ac88d2bd
https://github.com/dyninst/dyninst/commit/90cbd22e36a84ca88c242d047ea7bee8ac88d2bd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: 174d94c757b069c160562af71e1b73ebff1af7bc
https://github.com/dyninst/dyninst/commit/174d94c757b069c160562af71e1b73ebff1af7bc
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Incorrect plt entry
Commit: dfed7cd195703fed35cb7062fae73734e3662733
https://github.com/dyninst/dyninst/commit/dfed7cd195703fed35cb7062fae73734e3662733
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: a0dd6c0a6358a4114275ed1eb6e443d8e2aee357
https://github.com/dyninst/dyninst/commit/a0dd6c0a6358a4114275ed1eb6e443d8e2aee357
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix some bugs
Commit: 6402e0be7ea636103c20cd96c51c33fe51d080cf
https://github.com/dyninst/dyninst/commit/6402e0be7ea636103c20cd96c51c33fe51d080cf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: 4ecf50b70066f72302a5002aae9031717aa30506
https://github.com/dyninst/dyninst/commit/4ecf50b70066f72302a5002aae9031717aa30506
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix ROSE register conversion I forgot to change after rebase
Commit: 8619c0dea9fa5d6321c097ed963066363cd3e4ac
https://github.com/dyninst/dyninst/commit/8619c0dea9fa5d6321c097ed963066363cd3e4ac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: 14fbeea0d16c97fc1082488370f025baee5cde0c
https://github.com/dyninst/dyninst/commit/14fbeea0d16c97fc1082488370f025baee5cde0c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: 33fbe55c3e993bf728b9cd77bdda560e29453e49
https://github.com/dyninst/dyninst/commit/33fbe55c3e993bf728b9cd77bdda560e29453e49
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: c8eb1bde556c029876d9ead245cbd14bf88bd89d
https://github.com/dyninst/dyninst/commit/c8eb1bde556c029876d9ead245cbd14bf88bd89d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: 1dbc13bb49394e12ebdb59903abee9a74f3ef930
https://github.com/dyninst/dyninst/commit/1dbc13bb49394e12ebdb59903abee9a74f3ef930
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: 362674cb657918ae8b04dc71e724536ba433bebe
https://github.com/dyninst/dyninst/commit/362674cb657918ae8b04dc71e724536ba433bebe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: 211c9173c7b6ce63b20f3054ae13449631216376
https://github.com/dyninst/dyninst/commit/211c9173c7b6ce63b20f3054ae13449631216376
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: 1ca3d7342647472fe00ea21a0e74157e62d19d9c
https://github.com/dyninst/dyninst/commit/1ca3d7342647472fe00ea21a0e74157e62d19d9c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: af0fbbca153bc8fd43cc7075d359af6f6b9a9b85
https://github.com/dyninst/dyninst/commit/af0fbbca153bc8fd43cc7075d359af6f6b9a9b85
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: bcfc5cbc30c99eb827e808ebdf0b39292acbe3c0
https://github.com/dyninst/dyninst/commit/bcfc5cbc30c99eb827e808ebdf0b39292acbe3c0
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: ab4211dd274b27ca9e7cdc95a1f9b4c17ed4809c
https://github.com/dyninst/dyninst/commit/ab4211dd274b27ca9e7cdc95a1f9b4c17ed4809c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: db85b1060bc66cee88e4710185c79046cf09e71e
https://github.com/dyninst/dyninst/commit/db85b1060bc66cee88e4710185c79046cf09e71e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: a6e5b16d2d3b89f0596f7b62614cfbe6898a6500
https://github.com/dyninst/dyninst/commit/a6e5b16d2d3b89f0596f7b62614cfbe6898a6500
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: b32b8f2825a80f47bc79f4b0114299cdea46e8ee
https://github.com/dyninst/dyninst/commit/b32b8f2825a80f47bc79f4b0114299cdea46e8ee
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: 8395f56ac0d473f5846002b24e24b1631180b30b
https://github.com/dyninst/dyninst/commit/8395f56ac0d473f5846002b24e24b1631180b30b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: 5114c2e34f2ebbf6194a9f7115da791fec78f7dd
https://github.com/dyninst/dyninst/commit/5114c2e34f2ebbf6194a9f7115da791fec78f7dd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: 3e12affb71c30ea6a51070b26a3afc9a22f24f69
https://github.com/dyninst/dyninst/commit/3e12affb71c30ea6a51070b26a3afc9a22f24f69
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: 7fade7817d185fd1c584ade11b992c097509cdf9
https://github.com/dyninst/dyninst/commit/7fade7817d185fd1c584ade11b992c097509cdf9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: 73d438db42613461cb08e28a2ac3ad7dbf08ed18
https://github.com/dyninst/dyninst/commit/73d438db42613461cb08e28a2ac3ad7dbf08ed18
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: 4f63598d3fe3e6af6a8c7aac47c5511736282285
https://github.com/dyninst/dyninst/commit/4f63598d3fe3e6af6a8c7aac47c5511736282285
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: c1404193c99c5527ee5ab1a95b93a7cc61d9817f
https://github.com/dyninst/dyninst/commit/c1404193c99c5527ee5ab1a95b93a7cc61d9817f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: 7a99589cb0b11711bc6d1c47f689d38a1f79b3b8
https://github.com/dyninst/dyninst/commit/7a99589cb0b11711bc6d1c47f689d38a1f79b3b8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: c0f840c684edac13329339255917439749c09ea7
https://github.com/dyninst/dyninst/commit/c0f840c684edac13329339255917439749c09ea7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: 29941ff8ec7ddc0dd3e6154bd99c95d5b32c5aeb
https://github.com/dyninst/dyninst/commit/29941ff8ec7ddc0dd3e6154bd99c95d5b32c5aeb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: fd33560068e56e2f0a875d99b0e0e245d7491076
https://github.com/dyninst/dyninst/commit/fd33560068e56e2f0a875d99b0e0e245d7491076
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: 30b74f04a6c30c87a0dc13481cfe01a71d81dd0a
https://github.com/dyninst/dyninst/commit/30b74f04a6c30c87a0dc13481cfe01a71d81dd0a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
Log Message:
-----------
Add flag to compressed instructions generation
Commit: e1a0fc8d12b709100adcb0605b32ba5aaad0d75e
https://github.com/dyninst/dyninst/commit/e1a0fc8d12b709100adcb0605b32ba5aaad0d75e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/req.txt
Log Message:
-----------
Huge update
Commit: 67f8dc503b6c952d3b2bffd6991bc3b746dd85f9
https://github.com/dyninst/dyninst/commit/67f8dc503b6c952d3b2bffd6991bc3b746dd85f9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Split codegen into multiple of 16 bits
Commit: 36663fa77ddeb34fd1e19bc227576f76524b18ab
https://github.com/dyninst/dyninst/commit/36663fa77ddeb34fd1e19bc227576f76524b18ab
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix indexing issue
Commit: 831e39e5c7fbd09bc63d1e7f7c2888a90be6fe9b
https://github.com/dyninst/dyninst/commit/831e39e5c7fbd09bc63d1e7f7c2888a90be6fe9b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix RISC-V ret bugs
Commit: d3ae17b10c783ff5443f9898b702828c293b2c5c
https://github.com/dyninst/dyninst/commit/d3ae17b10c783ff5443f9898b702828c293b2c5c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Fix stack and instruction bugs
Commit: 8248ba1a2a0c7bb851be2c373a2b69d657d06f31
https://github.com/dyninst/dyninst/commit/8248ba1a2a0c7bb851be2c373a2b69d657d06f31
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix long branch bug
Commit: 7a6294aa59c95d028c84f0e37500d9fbd432b547
https://github.com/dyninst/dyninst/commit/7a6294aa59c95d028c84f0e37500d9fbd432b547
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add modifyData and fix auipc jalr bug
Commit: f65ca740ab7087294397ec509a30cae43b667e9e
https://github.com/dyninst/dyninst/commit/f65ca740ab7087294397ec509a30cae43b667e9e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M proccontrol/src/riscv_process.C
Log Message:
-----------
Add Marco's patch
Commit: fb0df8363fc34f2c38f80a0c3ef29f751be53287
https://github.com/dyninst/dyninst/commit/fb0df8363fc34f2c38f80a0c3ef29f751be53287
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Commit: bbbe51e224ac37787005a9c430eca2049b23fad3
https://github.com/dyninst/dyninst/commit/bbbe51e224ac37787005a9c430eca2049b23fad3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Patch RISC-V SAIL parser
Commit: 62966ad6e59b68674935702e0b05f1ff5cfbdeb9
https://github.com/dyninst/dyninst/commit/62966ad6e59b68674935702e0b05f1ff5cfbdeb9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Fix parse_riscv_attribute API
Commit: ea6cfe5948287bb03a64c71f9ee4bac8fd2005c4
https://github.com/dyninst/dyninst/commit/ea6cfe5948287bb03a64c71f9ee4bac8fd2005c4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
M parseAPI/src/IA_riscv64.C
M proccontrol/src/riscv_process.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Fix include arch-riscv64.h
Commit: 76cf446f3fc95e0bdda08004e0058d092d59773c
https://github.com/dyninst/dyninst/commit/76cf446f3fc95e0bdda08004e0058d092d59773c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Revert emitElfStatic-riscv64.C
Commit: 66c089163bf00e1380488beb8ce8dd3aed5cbb71
https://github.com/dyninst/dyninst/commit/66c089163bf00e1380488beb8ce8dd3aed5cbb71
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M proccontrol/src/riscv_process.C
Log Message:
-----------
Fix Object ELF
Commit: 95fda93eb9ac4a09a90ee6a16af8adaa2f561aa8
https://github.com/dyninst/dyninst/commit/95fda93eb9ac4a09a90ee6a16af8adaa2f561aa8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M parseAPI/h/CodeSource.h
M parseAPI/h/InstructionAdapter.h
M parseAPI/src/IA_IAPI.C
M parseAPI/src/IA_IAPI.h
M parseAPI/src/IA_riscv64.C
M parseAPI/src/Parser.C
M parseAPI/src/Parser.h
M parseAPI/src/ParserDetails.C
M parseAPI/src/SymtabCodeSource.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Solve RISC-V PLT issue
Commit: db1c5a499a9360288eec5860536566a93a9f971c
https://github.com/dyninst/dyninst/commit/db1c5a499a9360288eec5860536566a93a9f971c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
64 ->XLENBITS
Commit: 8b134db758331d2a7aa68aadf63f8a00c91aa280
https://github.com/dyninst/dyninst/commit/8b134db758331d2a7aa68aadf63f8a00c91aa280
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite constant constraints
Commit: aa0086dcc5c461ef1d81133b8e5542bedfda9d43
https://github.com/dyninst/dyninst/commit/aa0086dcc5c461ef1d81133b8e5542bedfda9d43
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Implement missing memory codegen and fix wrong emitImm
Commit: 554e1030bd06c403aa1a77cfc9f2afde6c4e68c4
https://github.com/dyninst/dyninst/commit/554e1030bd06c403aa1a77cfc9f2afde6c4e68c4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing instructions in instructionAPI
Commit: d3f5d25c0024fc15292af9a913c50baa94042ddd
https://github.com/dyninst/dyninst/commit/d3f5d25c0024fc15292af9a913c50baa94042ddd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix c.lui
Commit: f0d7a54c50321f67a063179b2a7eaa5cbcd00d85
https://github.com/dyninst/dyninst/commit/f0d7a54c50321f67a063179b2a7eaa5cbcd00d85
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Correct storing registers in emitCall
Commit: 1289141ad658efaa2ab00d3cffbac7e185edaddf
https://github.com/dyninst/dyninst/commit/1289141ad658efaa2ab00d3cffbac7e185edaddf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add missing atomic instruction in InstructionAPI
Commit: 600206189cc53198b653507fabdbc356495ae759
https://github.com/dyninst/dyninst/commit/600206189cc53198b653507fabdbc356495ae759
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix inter modular function address
Commit: df631ae7aaf88ae3e28d5644b79800f576b40bbe
https://github.com/dyninst/dyninst/commit/df631ae7aaf88ae3e28d5644b79800f576b40bbe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Add branch via trap for RISC-V
Commit: 3c51adb551c61140b9d61ea56dbf487ae59a793b
https://github.com/dyninst/dyninst/commit/3c51adb551c61140b9d61ea56dbf487ae59a793b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Pull register space from address space
Commit: a75b617c1b6f41b3cc237ca9e86a932963f94b3d
https://github.com/dyninst/dyninst/commit/a75b617c1b6f41b3cc237ca9e86a932963f94b3d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
Log Message:
-----------
Fix wrong ElfX_Dyn
Commit: 105527b05a61c1ab6a5f8153237d885318dbee18
https://github.com/dyninst/dyninst/commit/105527b05a61c1ab6a5f8153237d885318dbee18
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix call instruction codegen bugs
Commit: 8770df25c3952c2b8b2756ae83e4b8536ad877a3
https://github.com/dyninst/dyninst/commit/8770df25c3952c2b8b2756ae83e4b8536ad877a3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix lui signedness problem
Commit: 76c8dcbf5361c726bd89e566f91aae3c16557d2d
https://github.com/dyninst/dyninst/commit/76c8dcbf5361c726bd89e566f91aae3c16557d2d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Minor adjustment in RISCV emitElfStatic
Commit: dc9d3673cae5af62ee93ea0dae69d6c387fa3471
https://github.com/dyninst/dyninst/commit/dc9d3673cae5af62ee93ea0dae69d6c387fa3471
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add missing addressWidth
Commit: 3b551d14a6d12830444dedca82ee2e2b3f4ee8a5
https://github.com/dyninst/dyninst/commit/3b551d14a6d12830444dedca82ee2e2b3f4ee8a5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen.C
Log Message:
-----------
Variable length buffer
Commit: 9eab721a765e6fc419e619dbe59fdf50bd884913
https://github.com/dyninst/dyninst/commit/9eab721a765e6fc419e619dbe59fdf50bd884913
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix incorrect offset in emitCall and emitLoadShared
Commit: f05531409b92b70b17b9a8a384108d15c0b1e87e
https://github.com/dyninst/dyninst/commit/f05531409b92b70b17b9a8a384108d15c0b1e87e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
beq to bne
Commit: 99f5a50d7bb31002e6e0ddb493f62520bce87327
https://github.com/dyninst/dyninst/commit/99f5a50d7bb31002e6e0ddb493f62520bce87327
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M instructionAPI/src/InstructionDecoder-Capstone.C
Log Message:
-----------
Fix indentation
Commit: 10af1fe5f3fd496c5562166ce89a123eded760d6
https://github.com/dyninst/dyninst/commit/10af1fe5f3fd496c5562166ce89a123eded760d6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Improve immediate calculation algorithm
Commit: 27b2bb78e1c2126fb4cb26dbd5cb7310509c8af3
https://github.com/dyninst/dyninst/commit/27b2bb78e1c2126fb4cb26dbd5cb7310509c8af3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Remove optimization for relative load store
Commit: 242c98d707fc272ab8f6ef07add4e7dd9abafdf5
https://github.com/dyninst/dyninst/commit/242c98d707fc272ab8f6ef07add4e7dd9abafdf5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix conditional branch offset error
Commit: 62b9b4b193cdf890141a9cb40d0496a6b0773d33
https://github.com/dyninst/dyninst/commit/62b9b4b193cdf890141a9cb40d0496a6b0773d33
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix jump offset
Commit: e37b9bf380a70506d3bda89a7500e821aaddd3fb
https://github.com/dyninst/dyninst/commit/e37b9bf380a70506d3bda89a7500e821aaddd3fb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Fix jump target in emitIf
Commit: ba4e1cb3464ae78436817bf1fdb1ebc8ad04d692
https://github.com/dyninst/dyninst/commit/ba4e1cb3464ae78436817bf1fdb1ebc8ad04d692
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Tail Call
Commit: fd67666d8b0bfdb6c2b9b363b3bc8b519f9e06b9
https://github.com/dyninst/dyninst/commit/fd67666d8b0bfdb6c2b9b363b3bc8b519f9e06b9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix typo
Commit: c66c486cc8fbf2d9eff59bddfc1fedf2f53f3219
https://github.com/dyninst/dyninst/commit/c66c486cc8fbf2d9eff59bddfc1fedf2f53f3219
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
A dataflowAPI/sail/experimental/sail_semantics.json
A dataflowAPI/sail/experimental/sail_to_rose.pl
Log Message:
-----------
Add Experimental SAIL parser
Commit: 6832b4ffff51f050afe644aa7074ee54915a980e
https://github.com/dyninst/dyninst/commit/6832b4ffff51f050afe644aa7074ee54915a980e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
Log Message:
-----------
Support DYNINST_CODEGEN_ARCH_RISCV64
Commit: ac651b11200fb3cb02c826df8188c0c39c4326e8
https://github.com/dyninst/dyninst/commit/ac651b11200fb3cb02c826df8188c0c39c4326e8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-07-18 (Fri, 18 Jul 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M dyninstAPI_RT/src/RTlinux.c
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add missing CODEGEN
Compare: https://github.com/dyninst/dyninst/compare/a5bd8f71f18a...ac651b11200f
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