[DynInst_API:] [dyninst/dyninst] 10f328: Add RISC-V instruction mnemonics and registers

[wxrdnx <noreply@xxxxxxxxxx>]

  Branch: refs/heads/angushe/riscv-symtab-api
  Home:   https://github.com/dyninst/dyninst
  Commit: 10f328c5d491445b2682b2cd62027282074bb71f
      https://github.com/dyninst/dyninst/commit/10f328c5d491445b2682b2cd62027282074bb71f
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/CMakeLists.txt
    M common/h/Architecture.h
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    A common/h/mnemonics/riscv64_entryIDs.h
    A common/h/registers/riscv64_regs.h
    M common/src/registers/MachRegister.C
    M dataflowAPI/src/ExpressionConversionVisitor.C
    M dwarf/src/dwarfHandle.C
    M dwarf/src/registers/convert.C
    A dwarf/src/registers/riscv64.h
    M elf/src/Elf_X.C
    A external/rose/riscv64InstructionEnum.h
    M instructionAPI/capstone/import_mnemonics.py
    A instructionAPI/capstone/riscv64/mnemonics.py
    A instructionAPI/capstone/riscv64/registers.py
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/interrupts.C
    M instructionAPI/src/syscalls.C
    M parseAPI/src/SymbolicExpression.C
    M proccontrol/src/process.C

  Log Message:
  -----------
  Add RISC-V instruction mnemonics and registers


  Commit: d2eb9f2521405461dbcee2d54f0aee1f57a94d32
      https://github.com/dyninst/dyninst/commit/d2eb9f2521405461dbcee2d54f0aee1f57a94d32
  Author: wxrdnx <67510189+wxrdnx@xxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Use regClass for register type comparison

Co-authored-by: Tim Haines <thaines.astro@xxxxxxxxx>


  Commit: 6db2c2ae362fdce99d21e8b699e3cd9d5712ef42
      https://github.com/dyninst/dyninst/commit/6db2c2ae362fdce99d21e8b699e3cd9d5712ef42
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M instructionAPI/src/Instruction.C

  Log Message:
  -----------
  Add a blank line above Arch_riscv64 case


  Commit: 0203799c28d073f05df754245eb1b9f59ca2672e
      https://github.com/dyninst/dyninst/commit/0203799c28d073f05df754245eb1b9f59ca2672e
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Remove RISC-V check in isZeroFlag


  Commit: 1432b4a3d8a8218fc8bb4e0e286c71fa6624ce15
      https://github.com/dyninst/dyninst/commit/1432b4a3d8a8218fc8bb4e0e286c71fa6624ce15
  Author: wxrdnx <67510189+wxrdnx@xxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add CSR check in isFloatingPoint

Co-authored-by: Tim Haines <thaines.astro@xxxxxxxxx>


  Commit: 8ef98cb18f5eada195d539af5fdbd0d67f87adf2
      https://github.com/dyninst/dyninst/commit/8ef98cb18f5eada195d539af5fdbd0d67f87adf2
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/h/registers/riscv64_regs.h

  Log Message:
  -----------
  Update comments on f<N>_32, f<N>_64, and f<N> FPRs


  Commit: dc08246229c5d7809e6ce3f5ed3dc9d1d3d15c9b
      https://github.com/dyninst/dyninst/commit/dc08246229c5d7809e6ce3f5ed3dc9d1d3d15c9b
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/h/registers/riscv64_regs.h

  Log Message:
  -----------
  Make f<N>_32 and f<N>_64 aliases of f<N>


  Commit: 38d74bd1fd83e50d7de2037ced8086841480bfc0
      https://github.com/dyninst/dyninst/commit/38d74bd1fd83e50d7de2037ced8086841480bfc0
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  The size of FPRs should be 8


  Commit: e38bdfc373c01c2d858ac1a36b4c82164065e940
      https://github.com/dyninst/dyninst/commit/e38bdfc373c01c2d858ac1a36b4c82164065e940
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M tests/unit/MachRegister/base_registers/CMakeLists.txt
    A tests/unit/MachRegister/base_registers/riscv64.cpp

  Log Message:
  -----------
  Add RISC-V base register unit test


  Commit: 2b1df7f66e2965d5a7f6fccb645300cb3c92fab5
      https://github.com/dyninst/dyninst/commit/2b1df7f66e2965d5a7f6fccb645300cb3c92fab5
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Fix RISC-V base register


  Commit: b9d99f7b24e3412b892db0218389722d2ae78e10
      https://github.com/dyninst/dyninst/commit/b9d99f7b24e3412b892db0218389722d2ae78e10
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-06-15 (Sun, 15 Jun 2025)

  Changed paths:
    M symtabAPI/src/Object-elf.C
    M symtabAPI/src/Object-elf.h
    M symtabAPI/src/emitElf.C
    A symtabAPI/src/emitElfStatic-riscv64.C
    M symtabAPI/src/emitElfStatic.C
    A symtabAPI/src/relocationEntry-elf-riscv64.C

  Log Message:
  -----------
  Add RISC-V ELF parsing


Compare: https://github.com/dyninst/dyninst/compare/424845275820...b9d99f7b24e3

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