Branch: refs/heads/angushe/riscv
Home: https://github.com/dyninst/dyninst
Commit: 4b5a919a002f275bcc5103029ce04b2234c4ff7a
https://github.com/dyninst/dyninst/commit/4b5a919a002f275bcc5103029ce04b2234c4ff7a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M CMakeLists.txt
A cmake/tpls/DyninstCapstone.cmake
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Add CMake stub
Commit: b6b05345fedb29113ca4212776bc60d987c9950b
https://github.com/dyninst/dyninst/commit/b6b05345fedb29113ca4212776bc60d987c9950b
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A instructionAPI/capstone/import.py
A instructionAPI/capstone/x86.py
Log Message:
-----------
Make parameter the root directory in import script
Instead of specifying the file name, the user just points to the
directory and the script will grab the necessary files.
Commit: c6fce01c544f96c31746e6aff5c22be0b36fea72
https://github.com/dyninst/dyninst/commit/c6fce01c544f96c31746e6aff5c22be0b36fea72
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/capstone/import.py
M instructionAPI/capstone/x86.py
Log Message:
-----------
Alias faddp to fadd
Capstone only uses fadd. This does not modify the entryIDs yet.
Commit: ab8225d892531b4ddd038a0cac6ed37a68ca64dc
https://github.com/dyninst/dyninst/commit/ab8225d892531b4ddd038a0cac6ed37a68ca64dc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/capstone/import.py
Log Message:
-----------
Add mnemonic translation to import script
Commit: 4ee93fc742d63df92b77760e1fbfc495b0448642
https://github.com/dyninst/dyninst/commit/4ee93fc742d63df92b77760e1fbfc495b0448642
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A instructionAPI/src/x86/register-xlat.C
A instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
Add Capstone->Dyninst register translation
Commit: dafeceebd515f96479fd265a9f146fcd71c416a8
https://github.com/dyninst/dyninst/commit/dafeceebd515f96479fd265a9f146fcd71c416a8
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A instructionAPI/src/x86/mnemonic-xlat.C
A instructionAPI/src/x86/mnemonic-xlat.h
Log Message:
-----------
Add Capstone->Dyninst mnemonic translation
Commit: fd76857d8fc16054e6f7c9d3a2e00cb9712fe9af
https://github.com/dyninst/dyninst/commit/fd76857d8fc16054e6f7c9d3a2e00cb9712fe9af
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/x86/decoder.C
A instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add stub replacement for x86 decoder
Commit: 90a5827fd03f7eaa9521f69e49e5bdf3c67354f0
https://github.com/dyninst/dyninst/commit/90a5827fd03f7eaa9521f69e49e5bdf3c67354f0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add decoder ctor and dtor
There is one usage of Capstone per decoder. This should be threadsafe
as it doesn't make sense to use a decoder with multiple threads
simultaneously. See comments in ctor for why there are two Capstone
handles per decoder.
Commit: d9f5891a506a03d30fa51b3999bbca68e739ae85
https://github.com/dyninst/dyninst/commit/d9f5891a506a03d30fa51b3999bbca68e739ae85
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add decodeOpcode
Commit: 6e690cf676ee10c77e0d04c4cd90536305f3f6cc
https://github.com/dyninst/dyninst/commit/6e690cf676ee10c77e0d04c4cd90536305f3f6cc
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add note in decodeOperands
Commit: da046d14c13a7dfeb784c09e98af105890b2cb5e
https://github.com/dyninst/dyninst/commit/da046d14c13a7dfeb784c09e98af105890b2cb5e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Add doDelayedDecode
This is a copy/paste of Xiaozhu's implementation. It appears to be
incomplete (as per the comments).
Commit: 62911fc34487d6d08ce1095346ec8d3acfab2efd
https://github.com/dyninst/dyninst/commit/62911fc34487d6d08ce1095346ec8d3acfab2efd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
stub -- refactor
Commit: 8e90472d6fbac1f37fe3c7c7b7b5e354cb23f1f1
https://github.com/dyninst/dyninst/commit/8e90472d6fbac1f37fe3c7c7b7b5e354cb23f1f1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Use disassembler object in decode_operands
Commit: b5e4ba0a17f5bd5c1829ee2d128ebd4c85c1a090
https://github.com/dyninst/dyninst/commit/b5e4ba0a17f5bd5c1829ee2d128ebd4c85c1a090
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
M instructionAPI/src/x86/decoder.h
Log Message:
-----------
Refactor decode_operands
This makes it much easier to follow.
Commit: 619776bb92a76469bd74ef941e21ee31d4e4b202
https://github.com/dyninst/dyninst/commit/619776bb92a76469bd74ef941e21ee31d4e4b202
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add detailed comments about operand types
Commit: e50b853ca1c3fa8fe04d51f6199bde03d08f44e5
https://github.com/dyninst/dyninst/commit/e50b853ca1c3fa8fe04d51f6199bde03d08f44e5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use Instruction::makeReturnExpression
No need to reinvent the wheel.
Commit: b340969e92e654844d1316e3cd85bd23c62d96a5
https://github.com/dyninst/dyninst/commit/b340969e92e654844d1316e3cd85bd23c62d96a5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove redundant includes
Commit: 874ae3bc2978b4a91b0fd5477cefd40d6f3dd9cd
https://github.com/dyninst/dyninst/commit/874ae3bc2978b4a91b0fd5477cefd40d6f3dd9cd
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor handling of implicit registers
By giving the properties names rather than std::pairs, it makes it much
easier to read.
Commit: 7ecc3c5e5362225c4044bbc1dbc4d30a02f8bc3e
https://github.com/dyninst/dyninst/commit/7ecc3c5e5362225c4044bbc1dbc4d30a02f8bc3e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Include decoding of {e,r}flags
Commit: c61b9878a9bf0b513b815fd6bc57ea03e2512e31
https://github.com/dyninst/dyninst/commit/c61b9878a9bf0b513b815fd6bc57ea03e2512e31
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment for explicit operands
Commit: 85ffa70f05f2341debea700db987359bc96407c0
https://github.com/dyninst/dyninst/commit/85ffa70f05f2341debea700db987359bc96407c0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix explicit operands example
Commit: 065eb635ef9b21efd2064b49e8e24399fc951327
https://github.com/dyninst/dyninst/commit/065eb635ef9b21efd2064b49e8e24399fc951327
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove extraneous namespace qualifier
Commit: e43e2f6afd23709479c68a9c63b7e3d5c62019ba
https://github.com/dyninst/dyninst/commit/e43e2f6afd23709479c68a9c63b7e3d5c62019ba
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor is_call
The original code did the nested check, but didn't need to.
if(cat == c_BranchInsn || cat == c_CallInsn) {
isCFT = true;
if(cat == c_CallInsn) {
isCall = true;
}
}
is equivalent to
if(cat == c_CallInsn) {
isCall = true;
}
if(cat == c_BranchInsn || isCall) {
isCFT = true;
}
Commit: 173141d29453ddf2aa77d9d3d4d89f1aba3af6ac
https://github.com/dyninst/dyninst/commit/173141d29453ddf2aa77d9d3d4d89f1aba3af6ac
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix comment in expand_eflags
Commit: 2a35d8e457a4b7e8212e17f5c935458f1762ddec
https://github.com/dyninst/dyninst/commit/2a35d8e457a4b7e8212e17f5c935458f1762ddec
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/register-xlat.C
Log Message:
-----------
Fix comment for BND registers
Commit: 0b47eee01622a02415c14f7b2996f22a7d6e82cf
https://github.com/dyninst/dyninst/commit/0b47eee01622a02415c14f7b2996f22a7d6e82cf
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_reg
Commit: 2bd2bde0ee713d0ae3a7b86702226abe0aab240a
https://github.com/dyninst/dyninst/commit/2bd2bde0ee713d0ae3a7b86702226abe0aab240a
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Refactor isCFT in decode_imm
Commit: 779cf6cdef322ef898d14e698e9740dcc8fd075c
https://github.com/dyninst/dyninst/commit/779cf6cdef322ef898d14e698e9740dcc8fd075c
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed 64-bit values for immediates
Commit: 2a11ecb71b907d2cc96dd53156d02e2586d4e4a4
https://github.com/dyninst/dyninst/commit/2a11ecb71b907d2cc96dd53156d02e2586d4e4a4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Update comment for relative branch immediates
Commit: f95b47c3dd4edae57a87d0cffb80a44e6d6532ec
https://github.com/dyninst/dyninst/commit/f95b47c3dd4edae57a87d0cffb80a44e6d6532ec
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove error check on size_to_type
It has been updated to include all values used by Capstone.
Commit: d00074aa616dd48ab2d4377c92afd0b6f63a1e53
https://github.com/dyninst/dyninst/commit/d00074aa616dd48ab2d4377c92afd0b6f63a1e53
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Remove unneeded assert
Commit: 467be6d08db3329eba63e134259968bd17eb3874
https://github.com/dyninst/dyninst/commit/467be6d08db3329eba63e134259968bd17eb3874
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move is_call and is_cft to where they are used
Commit: 6ca4ec6d95c38e2c02fb131a5a2860ae48513e11
https://github.com/dyninst/dyninst/commit/6ca4ec6d95c38e2c02fb131a5a2860ae48513e11
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use signed values for calculations
The manual says everything but the scale can be positive or negative.
Commit: f1967c7f7c922cf3c69955dc00d6bdd01f3622cf
https://github.com/dyninst/dyninst/commit/f1967c7f7c922cf3c69955dc00d6bdd01f3622cf
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Use braces
Commit: 5a337f616633e6cf539ff6f606805bd2d61c0227
https://github.com/dyninst/dyninst/commit/5a337f616633e6cf539ff6f606805bd2d61c0227
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Move size_to_type to where it is used
Commit: d5d317378448e72d0130f8af9a85fdcdbbb3c9c1
https://github.com/dyninst/dyninst/commit/d5d317378448e72d0130f8af9a85fdcdbbb3c9c1
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add some whitespace
Commit: 16e9df3186a088c6b1d80aca0056186107d69e1e
https://github.com/dyninst/dyninst/commit/16e9df3186a088c6b1d80aca0056186107d69e1e
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add description from Intel manual
Commit: ecdf6de984ccecea002c70ee1e5efbe02367a87f
https://github.com/dyninst/dyninst/commit/ecdf6de984ccecea002c70ee1e5efbe02367a87f
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Return early if processing a CFT
Commit: d7c4a591b239a90783c3d006d3826e0ade281e94
https://github.com/dyninst/dyninst/commit/d7c4a591b239a90783c3d006d3826e0ade281e94
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Add comment about LEA
Commit: f0dc049182ce75ec4aa600850d55ad470eec88db
https://github.com/dyninst/dyninst/commit/f0dc049182ce75ec4aa600850d55ad470eec88db
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Rename immAST -> displacementAST
This better reflects its meaning.
Commit: dc3ae55f10fa69e1683a804055c8cf93dd14a8ab
https://github.com/dyninst/dyninst/commit/dc3ae55f10fa69e1683a804055c8cf93dd14a8ab
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Handle segment registers as memory operands
Commit: 544b77e8c0b0329f90cb61e6ebae090386b64be5
https://github.com/dyninst/dyninst/commit/544b77e8c0b0329f90cb61e6ebae090386b64be5
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Fix cmake formatting in instructionAPI/CMakeLists.txt
Commit: 07d71f5605ae858da387d6640f6e762d52f705ff
https://github.com/dyninst/dyninst/commit/07d71f5605ae858da387d6640f6e762d52f705ff
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M .github/workflows/dependency-version.yaml
M docker/dependencies.versions
Log Message:
-----------
Add dependency-version check for Capstone
Commit: 5cde2240684943ae343ef7090ee983f01ce4e85d
https://github.com/dyninst/dyninst/commit/5cde2240684943ae343ef7090ee983f01ce4e85d
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
Log Message:
-----------
Make Capstone a private dependency
Commit: 67700d8945a17fec300d387d0f779c9f4c0816d4
https://github.com/dyninst/dyninst/commit/67700d8945a17fec300d387d0f779c9f4c0816d4
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A docker/build_capstone.sh
M docker/dependencies.versions
Log Message:
-----------
Docker: add Capstone builds
Commit: 100b804e2f2270cb4a323c35604ef4c9c276d093
https://github.com/dyninst/dyninst/commit/100b804e2f2270cb4a323c35604ef4c9c276d093
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Only decode segment register operands for i386
Commit: 9a4e87b92c3dd1ac7bf87b2c6bf61ba88e7585d0
https://github.com/dyninst/dyninst/commit/9a4e87b92c3dd1ac7bf87b2c6bf61ba88e7585d0
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/x86/decoder.C
Log Message:
-----------
Fix format from clang's -Wformat-pedantic
Commit: 344a55ec6924d2f30258be164d5009bf453c5714
https://github.com/dyninst/dyninst/commit/344a55ec6924d2f30258be164d5009bf453c5714
Author: Tim Haines <thaines.astro@xxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M cmake/tpls/DyninstCapstone.cmake
Log Message:
-----------
Use correct capitalization for capstone_ROOT in CMake
Commit: 41b98054254ffe26eeb8455a962a44cfd083ddf1
https://github.com/dyninst/dyninst/commit/41b98054254ffe26eeb8455a962a44cfd083ddf1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/h/Architecture.h
M dwarf/src/dwarfHandle.C
Log Message:
-----------
Add riscv architecture
Commit: 6d8e6be0049d3ba4497aafc1540791fa09c5e879
https://github.com/dyninst/dyninst/commit/6d8e6be0049d3ba4497aafc1540791fa09c5e879
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A instructionAPI/capstone/capstone.py
M instructionAPI/capstone/import.py
A instructionAPI/capstone/riscv64.py
Log Message:
-----------
Add riscv64 capstone parser
Commit: 01571691cbc115b672314bd50d2c2e2940c98290
https://github.com/dyninst/dyninst/commit/01571691cbc115b672314bd50d2c2e2940c98290
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/CMakeLists.txt
M common/h/dyn_regs.h
M common/h/entryIDs.h
A common/h/mnemonics/riscv64_entryIDs.h
A common/h/registers/riscv64_regs.h
A common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
Log Message:
-----------
Add RISC-V registers and mnemonics
Commit: e30ba0a1f20dd58a74f44aa9c1f129769f113a5b
https://github.com/dyninst/dyninst/commit/e30ba0a1f20dd58a74f44aa9c1f129769f113a5b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M elf/src/Elf_X.C
M proccontrol/src/process.C
Log Message:
-----------
Add cases for Arch_riscv64 to suppress compiler warnings
Commit: afe4f8c466ea07f1b4f7c1365260a24555354d71
https://github.com/dyninst/dyninst/commit/afe4f8c466ea07f1b4f7c1365260a24555354d71
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
M instructionAPI/capstone/import.py
M instructionAPI/h/ArchSpecificFormatters.h
M instructionAPI/src/ArchSpecificFormatters.C
A instructionAPI/src/InstructionDecoder-Capstone.C
A instructionAPI/src/InstructionDecoder-Capstone.h
A instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/InstructionDecoderImpl.C
Log Message:
-----------
Add Capstone-based RISC-V InstructionAPI
Commit: 63d7b52b1c863392ff7eb97499ec9b5f885d1e5b
https://github.com/dyninst/dyninst/commit/63d7b52b1c863392ff7eb97499ec9b5f885d1e5b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M parseAPI/CMakeLists.txt
M parseAPI/src/CodeSource.C
M parseAPI/src/IA_IAPI.C
A parseAPI/src/IA_riscv64.C
A parseAPI/src/IA_riscv64.h
M parseAPI/src/SymbolicExpression.C
Log Message:
-----------
Add RISC-V ParseAPI
Commit: 45ab5cbd070349ac2d5fcc633fadc59c6946b534
https://github.com/dyninst/dyninst/commit/45ab5cbd070349ac2d5fcc633fadc59c6946b534
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A dataflowAPI/rose/SgAsmRiscv64Instruction.h
M dataflowAPI/rose/conversions.h
A dataflowAPI/rose/semantics/DispatcherRiscv64.C
A dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/Registers.h
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/RoseImpl.C
M dataflowAPI/src/RoseInsnFactory.C
M dataflowAPI/src/RoseInsnFactory.h
M dataflowAPI/src/SymEval.C
M dataflowAPI/src/SymbolicExpansion.C
M dataflowAPI/src/SymbolicExpansion.h
M dataflowAPI/src/convertOpcodes.C
A external/rose/riscv64InstructionEnum.h
M external/rose/rose-compat.h
Log Message:
-----------
Implement RISC-V DataflowAPI base code
Commit: 02bb2f2e6b44ccb296045daa35d5f5f5514d247c
https://github.com/dyninst/dyninst/commit/02bb2f2e6b44ccb296045daa35d5f5f5514d247c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A dataflowAPI/sail/riscv_sail_to_rose.pl
A dataflowAPI/sail/sail_ast.pl
A dataflowAPI/sail/sail_lex.pl
A dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add sail lexical parser
Commit: cc3f56e4276cd4316da53bc05191167104403dbb
https://github.com/dyninst/dyninst/commit/cc3f56e4276cd4316da53bc05191167104403dbb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
rewrite sail lexer using regex
Commit: 510bfbb2070e8688c8384478c2a40376a0257e57
https://github.com/dyninst/dyninst/commit/510bfbb2070e8688c8384478c2a40376a0257e57
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/sail/sail_lex.pl
Log Message:
-----------
Use array instead of hash
Commit: 840194a5310835d1ef0ba81bf9994454245906fb
https://github.com/dyninst/dyninst/commit/840194a5310835d1ef0ba81bf9994454245906fb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/sail/sail_syntax.pl
Log Message:
-----------
Add most syntax
Commit: 3a02607c1299599c182bc7e7441211a65a9afd33
https://github.com/dyninst/dyninst/commit/3a02607c1299599c182bc7e7441211a65a9afd33
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A dataflowAPI/sail/riscv_ast.json
R dataflowAPI/sail/riscv_sail_to_rose.pl
R dataflowAPI/sail/sail_ast.pl
R dataflowAPI/sail/sail_lex.pl
R dataflowAPI/sail/sail_syntax.pl
A dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (UTYPE)
Commit: d4eb32ab2be0d3d27403d6fa436f9c2e39bc0e93
https://github.com/dyninst/dyninst/commit/d4eb32ab2be0d3d27403d6fa436f9c2e39bc0e93
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/h/Architecture.h
Log Message:
-----------
Add missing riscv64 address width
Commit: 783ca5d319d4cc91ce6decebab2aad7ce8f6ca09
https://github.com/dyninst/dyninst/commit/783ca5d319d4cc91ce6decebab2aad7ce8f6ca09
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Add sail to rose converter (IMAC subsets)
Commit: cfb4dd53374d7008f7e96d95fa5baac105e4a4c9
https://github.com/dyninst/dyninst/commit/cfb4dd53374d7008f7e96d95fa5baac105e4a4c9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/src/ExpressionConversionVisitor.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Integrate riscv64 ROSE code into dataflowAPI
Commit: 97b93f2ae97c2244c8df25290d8d40da2eae18f5
https://github.com/dyninst/dyninst/commit/97b93f2ae97c2244c8df25290d8d40da2eae18f5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/CMakeLists.txt
R instructionAPI/src/x86/decoder.C
R instructionAPI/src/x86/decoder.h
R instructionAPI/src/x86/mnemonic-xlat.C
R instructionAPI/src/x86/mnemonic-xlat.h
R instructionAPI/src/x86/register-xlat.C
R instructionAPI/src/x86/register-xlat.h
Log Message:
-----------
migrate instructionAPI to capstone
Commit: 9789067fc64af452d13a3527926d3156b195ca24
https://github.com/dyninst/dyninst/commit/9789067fc64af452d13a3527926d3156b195ca24
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/BaseSemantics2.h
A dataflowAPI/rose/semantics/ConcreteSemantics2.C
A dataflowAPI/rose/semantics/ConcreteSemantics2.h
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dataflowAPI/rose/semantics/SymEvalSemantics.h
M dataflowAPI/src/SymEvalPolicy.h
Log Message:
-----------
fix mulhsu instruction semantic
Commit: dc6f0fc82a1dc1c7fce9e1fdf600147463cb7248
https://github.com/dyninst/dyninst/commit/dc6f0fc82a1dc1c7fce9e1fdf600147463cb7248
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M cmake/DyninstPlatform.cmake
M cmake/tpls/DyninstCapstone.cmake
M common/CMakeLists.txt
A common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/src/ABI.C
M dataflowAPI/src/RegisterMap.C
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
A dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget.h
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
A dyninstAPI/src/codegen-riscv64.C
A dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.h
A dyninstAPI/src/emit-riscv64.C
A dyninstAPI/src/emit-riscv64.h
A dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/mapped_object.C
A dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI/src/unix.C
M dyninstAPI_RT/CMakeLists.txt
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/CMakeLists.txt
M proccontrol/src/linux.C
M proccontrol/src/linux.h
A proccontrol/src/loadLibrary/codegen-riscv64.C
M proccontrol/src/loadLibrary/codegen.C
M proccontrol/src/loadLibrary/codegen.h
A proccontrol/src/riscv_process.C
A proccontrol/src/riscv_process.h
Log Message:
-----------
Add RISC-V guards
Commit: 46d839a42474778dc649e485b704829332a17970
https://github.com/dyninst/dyninst/commit/46d839a42474778dc649e485b704829332a17970
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/binaryEdit.C
M dyninstAPI/src/codegen.C
M dyninstAPI/src/function.h
M dyninstAPI/src/linux.C
M stackwalk/CMakeLists.txt
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/framestepper.C
A stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/linux-swk.C
A stackwalk/src/riscv64-swk.C
A stackwalk/src/riscv64-swk.h
M symtabAPI/CMakeLists.txt
M symtabAPI/src/emitElfStatic.C
Log Message:
-----------
Add RISC-V stackwalk guard
Commit: ad43320f674f48c79e725a9cbabb2b705cede636
https://github.com/dyninst/dyninst/commit/ad43320f674f48c79e725a9cbabb2b705cede636
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A dyninstAPI_RT/src/RTthread-riscv64.c
Log Message:
-----------
Add missing RTthread-riscv64.c
Commit: 3761b7fda7a6b992f531cb2fee1a24f185dcbb6f
https://github.com/dyninst/dyninst/commit/3761b7fda7a6b992f531cb2fee1a24f185dcbb6f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A symtabAPI/src/emitElfStatic-riscv64.C
A symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Create RISC-V emitter template
Commit: 7a75894e1524a2eea6c4b6a9d5fac9c469dcf82f
https://github.com/dyninst/dyninst/commit/7a75894e1524a2eea6c4b6a9d5fac9c469dcf82f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A dyninstAPI_RT/src/RTstatic_ctors_dtors-riscv64.c
Log Message:
-----------
Add missing RTstatic_ctors_dtors-riscv64.c
Commit: 0e5d1987fb1e420cf191885d493f9096aa7bd696
https://github.com/dyninst/dyninst/commit/0e5d1987fb1e420cf191885d493f9096aa7bd696
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dataflowAPI/src/RegisterMap.h
M dyninstAPI/CMakeLists.txt
M dyninstAPI/src/RegisterConversion-riscv64.C
A dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
A dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/inst-riscv64.C
A dyninstAPI/src/linux-riscv64.C
A dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI/src/registerSpace.h
A dyninstAPI/src/stackwalk-riscv64.C
M dyninstAPI/src/unix.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/dbginfo-stepper.C
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/src/emitElfStatic-stub.C
Log Message:
-----------
Make RISC-V dyninst compile on a RISC-V machine
Commit: 86b207ca365030ed6c79e8c885ef39d996c7c3d1
https://github.com/dyninst/dyninst/commit/86b207ca365030ed6c79e8c885ef39d996c7c3d1
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
Log Message:
-----------
Implement some instruction emission functions
Commit: f471bd0b8dbade59f73b9412baaf15295f0b4813
https://github.com/dyninst/dyninst/commit/f471bd0b8dbade59f73b9412baaf15295f0b4813
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M dataflowAPI/rose/semantics/Registers.C
M dataflowAPI/rose/semantics/SymEvalSemantics.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/registerSpace.h
M external/rose/riscv64InstructionEnum.h
Log Message:
-----------
Amalgamate 32 and 64 bit fpr
Commit: dbd535bd93966c625a9b83ffac20f0da24e99ff7
https://github.com/dyninst/dyninst/commit/dbd535bd93966c625a9b83ffac20f0da24e99ff7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Add emitImm
Commit: b5285630aa9443fb4699c91d2e5bb42910f0605b
https://github.com/dyninst/dyninst/commit/b5285630aa9443fb4699c91d2e5bb42910f0605b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/src/ABI.C
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/BPatch_snippet.C
M dyninstAPI/src/arch-forward-decl.h
M dyninstAPI/src/ast.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/legacy-instruction.h
M dyninstAPI/src/linux-riscv64.h
M dyninstAPI/src/linux.h
M dyninstAPI/src/registerSpace.C
M dyninstAPI/src/registerSpace.h
M dyninstAPI_RT/src/RTlinux.c
M proccontrol/src/linux.C
M stackwalk/src/dbginfo-stepper.C
Log Message:
-----------
Rename arch_riscv64 to DYNINST_HOST_ARCH_AARCH64
Commit: 50fd691344d5a83b651858a2a2147d80f1b9cfbb
https://github.com/dyninst/dyninst/commit/50fd691344d5a83b651858a2a2147d80f1b9cfbb
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/CMakeLists.txt
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/convert.C
A dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/convertOpcodes.C
M dwarf/CMakeLists.txt
M dwarf/src/registers/convert.C
A dwarf/src/registers/riscv64.h
M dyninstAPI/src/inst-riscv64.h
M external/rose/riscv64InstructionEnum.h
M parseAPI/CMakeLists.txt
Log Message:
-----------
Add missing RISC-V ROSE register conversion
Commit: 679d4a8098513d89e7a178ca671c70ab8764eaea
https://github.com/dyninst/dyninst/commit/679d4a8098513d89e7a178ca671c70ab8764eaea
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Add missing invalid operand check
Commit: 6687b49cc00d994877b334433c987e3f70a1012b
https://github.com/dyninst/dyninst/commit/6687b49cc00d994877b334433c987e3f70a1012b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-aarch64.C
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dataflowAPI/CMakeLists.txt
M dataflowAPI/rose/registers/riscv64.h
M dataflowAPI/src/RoseInsnFactory.h
M dyninstAPI/src/Parsing.h
M dyninstAPI/src/mapped_object.C
M instructionAPI/h/Instruction.h
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M instructionAPI/src/interrupts.C
M instructionAPI/src/syscalls.C
M parseAPI/CMakeLists.txt
M parseAPI/src/IA_riscv64.C
M stackwalk/CMakeLists.txt
M stackwalk/src/linux-riscv64-swk.C
M stackwalk/src/riscv64-swk.C
M symtabAPI/CMakeLists.txt
Log Message:
-----------
Modify RISC-V Capstone instruction decoder
Commit: 62fa8121cb28e5edd93a6ab9215f5e7ccf455206
https://github.com/dyninst/dyninst/commit/62fa8121cb28e5edd93a6ab9215f5e7ccf455206
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add C-Type Emitter
Commit: e46b7dbb77da27da7fd99a244704806405c8d97d
https://github.com/dyninst/dyninst/commit/e46b7dbb77da27da7fd99a244704806405c8d97d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add Load Immediate
Commit: fe447ba3b43b09d1ab64019ae9f6ea33d0a43cde
https://github.com/dyninst/dyninst/commit/fe447ba3b43b09d1ab64019ae9f6ea33d0a43cde
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Change insn_size to is_compressed
Commit: dbdbd2ebeb2d454424545e5d8444a9d3fc21de7a
https://github.com/dyninst/dyninst/commit/dbdbd2ebeb2d454424545e5d8444a9d3fc21de7a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add addi codegen
Commit: 4ff5c3ee03ef53cf324b7899cb71b27bb49aca3a
https://github.com/dyninst/dyninst/commit/4ff5c3ee03ef53cf324b7899cb71b27bb49aca3a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Optimize addi Code Generation
Commit: 51bc4004bd6507b244240aeb5c6446ca1422d1f3
https://github.com/dyninst/dyninst/commit/51bc4004bd6507b244240aeb5c6446ca1422d1f3
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M cmake/DyninstCapArchDef.cmake
M dyninstAPI/CMakeLists.txt
M dyninstAPI_RT/CMakeLists.txt
Log Message:
-----------
Fix DYNINST_ARCH_riscv64
Commit: 2daf759e93bf304112f4940d87d28d390c786a00
https://github.com/dyninst/dyninst/commit/2daf759e93bf304112f4940d87d28d390c786a00
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/src/ABI.C
Log Message:
-----------
Add RISC-V initialize64
Commit: 98610208ddaf29a4aac66d16509cd04a33097d04
https://github.com/dyninst/dyninst/commit/98610208ddaf29a4aac66d16509cd04a33097d04
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/h/registers/riscv64_regs.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Parsing-arch.C
M dyninstAPI/src/RegisterConversion-riscv64.C
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-aarch64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/parse-cfg.h
M dyninstAPI/src/parse-riscv64.C
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/CMakeLists.txt
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Rebase and fix code generation
Commit: a537a5df5a8f4bf2be052caa254710357edc5523
https://github.com/dyninst/dyninst/commit/a537a5df5a8f4bf2be052caa254710357edc5523
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V jump instruction generation
Commit: 4a509e2ad59535d75c3ed38b920f6f7b7a8fc24a
https://github.com/dyninst/dyninst/commit/4a509e2ad59535d75c3ed38b920f6f7b7a8fc24a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI_RT/src/RTlinux.c
M stackwalk/src/linux-riscv64-swk.C
Log Message:
-----------
Change gregs to __gregs
Commit: a22f4e2b988076febed1144d2f2a7c7cef980657
https://github.com/dyninst/dyninst/commit/a22f4e2b988076febed1144d2f2a7c7cef980657
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Add RISC-V Long Branch
Commit: dc0b6c7af243d748438eb17edc4b7c854d627b7f
https://github.com/dyninst/dyninst/commit/dc0b6c7af243d748438eb17edc4b7c854d627b7f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite shifts and constants in RISC-V codegen
Commit: 76613b4968088b2baf643528136edafab13c38bf
https://github.com/dyninst/dyninst/commit/76613b4968088b2baf643528136edafab13c38bf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix wrong indexing order in INSN_SET
Commit: d8b720504a25c53e8a92cfd34b777d4c5a5c363b
https://github.com/dyninst/dyninst/commit/d8b720504a25c53e8a92cfd34b777d4c5a5c363b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Rewrite load and store using I-Type and S-Type generator
Commit: 30a3e87ac54f764154437491effbea4802060d85
https://github.com/dyninst/dyninst/commit/30a3e87ac54f764154437491effbea4802060d85
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Finish emit basic operators
Commit: f14be712dd138898c29ad64ac8fff38faa68c589
https://github.com/dyninst/dyninst/commit/f14be712dd138898c29ad64ac8fff38faa68c589
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
Log Message:
-----------
Add conditional branch
Commit: 5a49cdcab136d62eee3968d9fda6b23addec0771
https://github.com/dyninst/dyninst/commit/5a49cdcab136d62eee3968d9fda6b23addec0771
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish emit-riscv64.C
Commit: 6a4cf8c11bc8ddca42b0c3ee6169c797cede2fb7
https://github.com/dyninst/dyninst/commit/6a4cf8c11bc8ddca42b0c3ee6169c797cede2fb7
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M common/src/registers/MachRegister.C
M dataflowAPI/rose/registers/convert.C
M dataflowAPI/rose/registers/riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Finish inst-riscv64.C
Commit: f088a1225637192604ca453bd2a831d488aaf1bd
https://github.com/dyninst/dyninst/commit/f088a1225637192604ca453bd2a831d488aaf1bd
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
Log Message:
-----------
Rewrite RISC-V Branch
Commit: 1d322e46424662f4995c823800b8a3d9f3fa9827
https://github.com/dyninst/dyninst/commit/1d322e46424662f4995c823800b8a3d9f3fa9827
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Make dyninstAPI compile
Commit: 02900e967850dcc72f9bf46554edb4e8a0527214
https://github.com/dyninst/dyninst/commit/02900e967850dcc72f9bf46554edb4e8a0527214
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/registers/MachRegister.C
Log Message:
-----------
Update MachRegister
Commit: 39db78417dc1edd7ac3e45c70abe192fe118e251
https://github.com/dyninst/dyninst/commit/39db78417dc1edd7ac3e45c70abe192fe118e251
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M parseAPI/h/CFGModifier.h
M parseAPI/src/BoundFactCalculator.C
Log Message:
-----------
Fixed missing RISC-V BoundFact
Commit: 87c946dd5ca43028cda311f717525d764dd2ab7f
https://github.com/dyninst/dyninst/commit/87c946dd5ca43028cda311f717525d764dd2ab7f
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Incorrect plt entry
Commit: f53a767d6113f259b3a201526dfb1063e76dda20
https://github.com/dyninst/dyninst/commit/f53a767d6113f259b3a201526dfb1063e76dda20
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
A instructionAPI/src/.gdb_history
M instructionAPI/src/InstructionCategories.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix RISC-V bugs in Instruction API
Commit: 204c3c2e57b66f2685d9c2829510ea4c4a04f980
https://github.com/dyninst/dyninst/commit/204c3c2e57b66f2685d9c2829510ea4c4a04f980
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
M instructionAPI/h/Operation_impl.h
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-Capstone.h
M instructionAPI/src/InstructionDecoder-riscv64.C
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix some bugs
Commit: f059ea049fefd4216fc6a61b6536c00f76a667ab
https://github.com/dyninst/dyninst/commit/f059ea049fefd4216fc6a61b6536c00f76a667ab
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix Segfault in pointer casting
Commit: e46f547781dda63c6fb66c331a9dd463e1531933
https://github.com/dyninst/dyninst/commit/e46f547781dda63c6fb66c331a9dd463e1531933
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/registers/riscv64.h
Log Message:
-----------
Fix ROSE register conversion I forgot to change after rebase
Commit: 53ee570d2461722ded3567b50f82fc8c5d5ff6ac
https://github.com/dyninst/dyninst/commit/53ee570d2461722ded3567b50f82fc8c5d5ff6ac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/Instruction.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Add register massaging to jalr
Commit: df17c7ac8331072ebeb22724c6044ecdb0812971
https://github.com/dyninst/dyninst/commit/df17c7ac8331072ebeb22724c6044ecdb0812971
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
M dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C
M dyninstAPI/src/registerSpace.h
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Fix jr instruction and incorrect fp
Commit: 1d1c50b02b01e006b8bdaf822674affcd07fdff8
https://github.com/dyninst/dyninst/commit/1d1c50b02b01e006b8bdaf822674affcd07fdff8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Revert wrong readRegister fix
Commit: c9b5f2e013152c6324ce2ca7f206d57cef418059
https://github.com/dyninst/dyninst/commit/c9b5f2e013152c6324ce2ca7f206d57cef418059
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M instructionAPI/src/Instruction.C
M parseAPI/src/IA_riscv64.C
Log Message:
-----------
Fix isReturn bug
Commit: 844a7eedf6c0a31f854b927c913bb091d642e928
https://github.com/dyninst/dyninst/commit/844a7eedf6c0a31f854b927c913bb091d642e928
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/src/RegisterMap.C
Log Message:
-----------
Fixed ud2 in RegisterMap
Commit: afcb81546809b69c1156ee78ce9349a250ce93bf
https://github.com/dyninst/dyninst/commit/afcb81546809b69c1156ee78ce9349a250ce93bf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Add riscv attribute
Commit: 5eeb0eabac7d6de13054c5acbd950b3790c9ec14
https://github.com/dyninst/dyninst/commit/5eeb0eabac7d6de13054c5acbd950b3790c9ec14
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Make Dyninst recognize .riscv.attributes
Commit: eda865edab98ae9b9b9e5f6ea3f145ad59dded3b
https://github.com/dyninst/dyninst/commit/eda865edab98ae9b9b9e5f6ea3f145ad59dded3b
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix bug parsing .riscv.attributes
Commit: e4131d60fd03be52e17e81d85ad17d10187fbdfe
https://github.com/dyninst/dyninst/commit/e4131d60fd03be52e17e81d85ad17d10187fbdfe
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
Fix incorrect relocation category
Commit: b4c67c2b238abc80eca0388022d29f1e7e828c50
https://github.com/dyninst/dyninst/commit/b4c67c2b238abc80eca0388022d29f1e7e828c50
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Don't know why I missed getRelTypeByElfMachine
Commit: 52a3944160dddda210085ccb443f4bde35ca9626
https://github.com/dyninst/dyninst/commit/52a3944160dddda210085ccb443f4bde35ca9626
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/relocationEntry-elf-riscv64.C
Log Message:
-----------
ifdef for libelf compatilibity
Commit: b5bb4b135cf756309a77088e02cd7210942f604e
https://github.com/dyninst/dyninst/commit/b5bb4b135cf756309a77088e02cd7210942f604e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add library adjust
Commit: efc580dcfc11b15904665f56154dfd773c3134c2
https://github.com/dyninst/dyninst/commit/efc580dcfc11b15904665f56154dfd773c3134c2
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/emitElf.C
Log Message:
-----------
Add preinit array
Commit: 8db24c761919103dcea617c654f747a40c63e16d
https://github.com/dyninst/dyninst/commit/8db24c761919103dcea617c654f747a40c63e16d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/emitElf.C
Log Message:
-----------
Fix incorrect uleb128 parsing
Commit: 73a1618e8f130121de5cd457b25991edd2cfdbe4
https://github.com/dyninst/dyninst/commit/73a1618e8f130121de5cd457b25991edd2cfdbe4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
Log Message:
-----------
Fix tag variable shadowing
Commit: 5cce8b26ba2b20ab405400d6c6f7318009c551b9
https://github.com/dyninst/dyninst/commit/5cce8b26ba2b20ab405400d6c6f7318009c551b9
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/emitElf.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Null instrumentation now works
Commit: 61f6218914378bc4c86641aa2e0806abf488fe91
https://github.com/dyninst/dyninst/commit/61f6218914378bc4c86641aa2e0806abf488fe91
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix incorrect parentheses and generateLoadImm
Commit: 7f044ee492337c74f23f122f90ecb7769b6a1076
https://github.com/dyninst/dyninst/commit/7f044ee492337c74f23f122f90ecb7769b6a1076
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
is_compressed should be true for C instructions
Commit: 2b7ef15094a4db4218005aa041839f12153b19ae
https://github.com/dyninst/dyninst/commit/2b7ef15094a4db4218005aa041839f12153b19ae
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/src/RoseInsnFactory.C
Log Message:
-----------
Fix inconsistency between Capstone and ROSE
Commit: dd0576912556d8f2f84e2020717afc5e9201ebb6
https://github.com/dyninst/dyninst/commit/dd0576912556d8f2f84e2020717afc5e9201ebb6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/rose/semantics/DispatcherRiscv64.h
M dataflowAPI/src/RoseInsnFactory.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Hardwire x0 to 0
Commit: 930f6fecf08219c68c6d729a0e557467f131813e
https://github.com/dyninst/dyninst/commit/930f6fecf08219c68c6d729a0e557467f131813e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-aarch64.C
Log Message:
-----------
Readd disappeared codegen in aarch64
Commit: ddb61542f5e9345add50d21adecc4c1c691a261c
https://github.com/dyninst/dyninst/commit/ddb61542f5e9345add50d21adecc4c1c691a261c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
emitLoadRelative and emitStoreRelative should be implemented
Commit: d6dc0bfa54cfc86b127ef929f7f716ea20a3046a
https://github.com/dyninst/dyninst/commit/d6dc0bfa54cfc86b127ef929f7f716ea20a3046a
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
remove evil constants
Commit: 76e6cb048f98b39857538f1efe7ef8ace234eba5
https://github.com/dyninst/dyninst/commit/76e6cb048f98b39857538f1efe7ef8ace234eba5
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
Log Message:
-----------
RISC-V CFWidget
Commit: 03575de8113cc3ca6b11e2aa6fd37552ba5afcb6
https://github.com/dyninst/dyninst/commit/03575de8113cc3ca6b11e2aa6fd37552ba5afcb6
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
Log Message:
-----------
RISC-V PCWidget
Commit: 6ed748d8232d7880960c73836d93c64598506434
https://github.com/dyninst/dyninst/commit/6ed748d8232d7880960c73836d93c64598506434
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
Log Message:
-----------
Add flag to compressed instructions generation
Commit: 9e3ab5b82f32b03155081b4c3c09b814f57c2638
https://github.com/dyninst/dyninst/commit/9e3ab5b82f32b03155081b4c3c09b814f57c2638
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/Relocation/Widgets/PCWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/codegen.C
M dyninstAPI/src/codegen.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/emit-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
A dyninstAPI/src/req.txt
Log Message:
-----------
Huge update
Commit: 4f7aa924bb23c851610f0b43824f5db0f3cede06
https://github.com/dyninst/dyninst/commit/4f7aa924bb23c851610f0b43824f5db0f3cede06
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-aarch64.h
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Split codegen into multiple of 16 bits
Commit: eb07fd25f1d5845814166ab77c130b18369f74c8
https://github.com/dyninst/dyninst/commit/eb07fd25f1d5845814166ab77c130b18369f74c8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
Log Message:
-----------
Fix indexing issue
Commit: 21b0e736c773a8d23133bc4016d87627234b63ac
https://github.com/dyninst/dyninst/commit/21b0e736c773a8d23133bc4016d87627234b63ac
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/inst-riscv64.C
Log Message:
-----------
Fix RISC-V ret bugs
Commit: 42cbda060a4199bc98dedf118567839273482cc4
https://github.com/dyninst/dyninst/commit/42cbda060a4199bc98dedf118567839273482cc4
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Fix stack and instruction bugs
Commit: e2135d6082da703d76bd9ffcf9219d27b59d4f83
https://github.com/dyninst/dyninst/commit/e2135d6082da703d76bd9ffcf9219d27b59d4f83
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/Relocation/Widgets/CFWidget-riscv64.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
Log Message:
-----------
Fix long branch bug
Commit: 281b88a1534ea8c98e14420bfb5574769db00b4c
https://github.com/dyninst/dyninst/commit/281b88a1534ea8c98e14420bfb5574769db00b4c
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/inst-riscv64.h
Log Message:
-----------
Add modifyData and fix auipc jalr bug
Commit: 45e69021f0bf995a33ae73d3d791bdcb42ba74c8
https://github.com/dyninst/dyninst/commit/45e69021f0bf995a33ae73d3d791bdcb42ba74c8
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M common/src/arch-riscv64.C
M common/src/arch-riscv64.h
M proccontrol/src/riscv_process.C
Log Message:
-----------
Add Marco's patch
Commit: 71dd0c4cdb839135e7f9dac0a4a23a7550659d7d
https://github.com/dyninst/dyninst/commit/71dd0c4cdb839135e7f9dac0a4a23a7550659d7d
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M instructionAPI/src/InstructionDecoder-riscv64.C
Log Message:
-----------
Change PC to read PC register
Commit: 7816d2f5f0ee35e8ff55325c6fa0474243fe9d87
https://github.com/dyninst/dyninst/commit/7816d2f5f0ee35e8ff55325c6fa0474243fe9d87
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dataflowAPI/rose/semantics/DispatcherRiscv64.C
M dataflowAPI/sail/sail_to_rose.pl
Log Message:
-----------
Patch RISC-V SAIL parser
Commit: b64e3be599f9a8da9e81203503dcd08f129f22bf
https://github.com/dyninst/dyninst/commit/b64e3be599f9a8da9e81203503dcd08f129f22bf
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M symtabAPI/src/Object-elf.C
M symtabAPI/src/Object-elf.h
Log Message:
-----------
Fix parse_riscv_attribute API
Commit: a1d6aeb3680dd418ef8b203b2b06204bb9d56f0e
https://github.com/dyninst/dyninst/commit/a1d6aeb3680dd418ef8b203b2b06204bb9d56f0e
Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
Date: 2025-04-15 (Tue, 15 Apr 2025)
Changed paths:
M dyninstAPI/src/BPatch_memoryAccessAdapter.C
M dyninstAPI/src/codegen-riscv64.C
M dyninstAPI/src/codegen-riscv64.h
M dyninstAPI/src/emit-riscv64.C
M dyninstAPI/src/inst-riscv64.C
M dyninstAPI/src/linux-riscv64.C
M dyninstAPI/src/parse-riscv64.C
M parseAPI/src/IA_riscv64.C
M proccontrol/src/riscv_process.C
M symtabAPI/src/emitElfStatic-riscv64.C
Log Message:
-----------
Fix include arch-riscv64.h
Compare: https://github.com/dyninst/dyninst/compare/b448b712efa9...a1d6aeb3680d
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