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[DynInst_API:] [dyninst/dyninst] 2619a1: Hardwire x0 to 0

Date: Sat, 15 Mar 2025 14:13:21 -0700
From: wxrdnx <noreply@xxxxxxxxxx>
Subject: [DynInst_API:] [dyninst/dyninst] 2619a1: Hardwire x0 to 0 
  Branch: refs/heads/angushe/riscv
  Home:   https://github.com/dyninst/dyninst
  Commit: 2619a1fd9185fbfb412e2870eed596858ab8940b
      https://github.com/dyninst/dyninst/commit/2619a1fd9185fbfb412e2870eed596858ab8940b
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-03-15 (Sat, 15 Mar 2025)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherRiscv64.C
    M dataflowAPI/rose/semantics/DispatcherRiscv64.h
    M dataflowAPI/src/RoseInsnFactory.C
    M instructionAPI/src/InstructionDecoder-riscv64.C

  Log Message:
  -----------
  Hardwire x0 to 0



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