[DynInst_API:] [dyninst/dyninst] b82ec9: Add RISC-V instruction mnemonics and registers

[wxrdnx <noreply@xxxxxxxxxx>]

  Branch: refs/heads/angushe/riscv-symtab-api
  Home:   https://github.com/dyninst/dyninst
  Commit: b82ec9e9d406aeca67d971fde559929b7aaa8b00
      https://github.com/dyninst/dyninst/commit/b82ec9e9d406aeca67d971fde559929b7aaa8b00
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/CMakeLists.txt
    M common/h/Architecture.h
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    A common/h/mnemonics/riscv64_entryIDs.h
    A common/h/registers/riscv64_regs.h
    M common/src/registers/MachRegister.C
    M dataflowAPI/src/ExpressionConversionVisitor.C
    M dwarf/src/dwarfHandle.C
    M dwarf/src/registers/convert.C
    A dwarf/src/registers/riscv64.h
    M elf/src/Elf_X.C
    A external/rose/riscv64InstructionEnum.h
    M instructionAPI/capstone/import_mnemonics.py
    A instructionAPI/capstone/riscv64/mnemonics.py
    A instructionAPI/capstone/riscv64/registers.py
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/interrupts.C
    M instructionAPI/src/syscalls.C
    M parseAPI/src/SymbolicExpression.C
    M proccontrol/src/process.C

  Log Message:
  -----------
  Add RISC-V instruction mnemonics and registers


  Commit: 60fa9e390137c95225c4b824c00c1dad79b565b2
      https://github.com/dyninst/dyninst/commit/60fa9e390137c95225c4b824c00c1dad79b565b2
  Author: wxrdnx <67510189+wxrdnx@xxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Use regClass for register type comparison

Co-authored-by: Tim Haines <thaines.astro@xxxxxxxxx>


  Commit: f6b878e41d7e399e64750225f9ab6828df6e5dd3
      https://github.com/dyninst/dyninst/commit/f6b878e41d7e399e64750225f9ab6828df6e5dd3
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M instructionAPI/src/Instruction.C

  Log Message:
  -----------
  Add a blank line above Arch_riscv64 case


  Commit: 146dcb776e31f91d279c6f76838f72c4156db637
      https://github.com/dyninst/dyninst/commit/146dcb776e31f91d279c6f76838f72c4156db637
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Remove RISC-V check in isZeroFlag


  Commit: 0fdd129b17329e1b5bd8736737b29299346803ca
      https://github.com/dyninst/dyninst/commit/0fdd129b17329e1b5bd8736737b29299346803ca
  Author: wxrdnx <67510189+wxrdnx@xxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add CSR check in isFloatingPoint

Co-authored-by: Tim Haines <thaines.astro@xxxxxxxxx>


  Commit: 3256e403b193b3ae3fb0bbca63e130275922647a
      https://github.com/dyninst/dyninst/commit/3256e403b193b3ae3fb0bbca63e130275922647a
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/h/registers/riscv64_regs.h

  Log Message:
  -----------
  Update comments on f<N>_32, f<N>_64, and f<N> FPRs


  Commit: 0059a532d43d66d0078348cfcb46f0d126b68ea9
      https://github.com/dyninst/dyninst/commit/0059a532d43d66d0078348cfcb46f0d126b68ea9
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/h/registers/riscv64_regs.h

  Log Message:
  -----------
  Make f<N>_32 and f<N>_64 aliases of f<N>


  Commit: 2c79c9fe57e59c354afae0a5cd507ac65cb79ec5
      https://github.com/dyninst/dyninst/commit/2c79c9fe57e59c354afae0a5cd507ac65cb79ec5
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  The size of FPRs should be 8


  Commit: 9765869f5055debbce1c487c82ae4adb402b7031
      https://github.com/dyninst/dyninst/commit/9765869f5055debbce1c487c82ae4adb402b7031
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M tests/MachRegister/base_registers/CMakeLists.txt
    A tests/MachRegister/base_registers/riscv64.cpp

  Log Message:
  -----------
  Add RISC-V base register unit test


  Commit: 4248452758204b6983a2890d192b949ba258fefc
      https://github.com/dyninst/dyninst/commit/4248452758204b6983a2890d192b949ba258fefc
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2025-02-27 (Thu, 27 Feb 2025)

  Changed paths:
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Fix RISC-V base register


Compare: https://github.com/dyninst/dyninst/compare/0775268dffac...424845275820

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