[DynInst_API:] [dyninst/dyninst] 5655a1: Add missing riscv64 address width

[wxrdnx <noreply@xxxxxxxxxx>]

  Branch: refs/heads/angushe/riscv
  Home:   https://github.com/dyninst/dyninst
  Commit: 5655a1dedcd71a5072b8ba7fbf75dda5d924e516
      https://github.com/dyninst/dyninst/commit/5655a1dedcd71a5072b8ba7fbf75dda5d924e516
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-10-28 (Mon, 28 Oct 2024)

  Changed paths:
    M common/h/Architecture.h

  Log Message:
  -----------
  Add missing riscv64 address width


  Commit: 8de5aaccf3a9d4343e182c09fa57251db5647fa3
      https://github.com/dyninst/dyninst/commit/8de5aaccf3a9d4343e182c09fa57251db5647fa3
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-10-28 (Mon, 28 Oct 2024)

  Changed paths:
    M dataflowAPI/sail/sail_to_rose.pl

  Log Message:
  -----------
  Add sail to rose converter (IMAC subsets)


  Commit: 51ca28aa729492b8af2f1bceeddbbd14e220217a
      https://github.com/dyninst/dyninst/commit/51ca28aa729492b8af2f1bceeddbbd14e220217a
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-10-28 (Mon, 28 Oct 2024)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherRiscv64.C
    M dataflowAPI/rose/semantics/DispatcherRiscv64.h
    M dataflowAPI/rose/semantics/Registers.C
    M dataflowAPI/src/ExpressionConversionVisitor.C
    M instructionAPI/src/InstructionDecoder-riscv64.C

  Log Message:
  -----------
  Integrate riscv64 ROSE code into dataflowAPI


Compare: https://github.com/dyninst/dyninst/compare/581cd89eaa52...51ca28aa7294

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