[DynInst_API:] [dyninst/dyninst] ed426a: Add riscv architecture

[wxrdnx <noreply@xxxxxxxxxx>]

  Branch: refs/heads/angushe/riscv_capstone_sail
  Home:   https://github.com/dyninst/dyninst
  Commit: ed426a226febdd50907108d02f2664555833d547
      https://github.com/dyninst/dyninst/commit/ed426a226febdd50907108d02f2664555833d547
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-23 (Fri, 23 Aug 2024)

  Changed paths:
    M common/h/Architecture.h
    M dwarf/src/dwarfHandle.C

  Log Message:
  -----------
  Add riscv architecture


  Commit: b1b64fcce229bc42d2ad900c4469e623f40f22b1
      https://github.com/dyninst/dyninst/commit/b1b64fcce229bc42d2ad900c4469e623f40f22b1
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-23 (Fri, 23 Aug 2024)

  Changed paths:
    M instructionAPI/capstone/capstone.py
    M instructionAPI/capstone/import.py
    A instructionAPI/capstone/riscv64.py

  Log Message:
  -----------
  Add riscv64 capstone parser


  Commit: d7c799bcfaec221f4a4fb629e9e45c019d985233
      https://github.com/dyninst/dyninst/commit/d7c799bcfaec221f4a4fb629e9e45c019d985233
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-25 (Sun, 25 Aug 2024)

  Changed paths:
    M common/CMakeLists.txt
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    A common/h/mnemonics/riscv64_entryIDs.h
    A common/h/registers/riscv64_regs.h
    A common/src/arch-riscv64.h
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add RISC-V registers and mnemonics


  Commit: 67e7e5d73c24d007cae05a2b4fa4fca693df4016
      https://github.com/dyninst/dyninst/commit/67e7e5d73c24d007cae05a2b4fa4fca693df4016
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-25 (Sun, 25 Aug 2024)

  Changed paths:
    M elf/src/Elf_X.C
    M proccontrol/src/process.C

  Log Message:
  -----------
  Add cases for Arch_riscv64 to suppress compiler warnings


  Commit: fc2e87c4f13ace5afde1afa583cae8290b1970fc
      https://github.com/dyninst/dyninst/commit/fc2e87c4f13ace5afde1afa583cae8290b1970fc
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-25 (Sun, 25 Aug 2024)

  Changed paths:
    M instructionAPI/CMakeLists.txt
    M instructionAPI/capstone/import.py
    M instructionAPI/h/ArchSpecificFormatters.h
    M instructionAPI/h/Instruction.h
    M instructionAPI/src/ArchSpecificFormatters.C
    M instructionAPI/src/InstructionCategories.C
    A instructionAPI/src/InstructionDecoder-Capstone.C
    A instructionAPI/src/InstructionDecoder-Capstone.h
    A instructionAPI/src/InstructionDecoder-riscv64.C
    M instructionAPI/src/InstructionDecoderImpl.C

  Log Message:
  -----------
  Add Capstone-based RISC-V InstructionAPI


  Commit: 69c5932c8569020592701d8dca742d80c3ef9ec3
      https://github.com/dyninst/dyninst/commit/69c5932c8569020592701d8dca742d80c3ef9ec3
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-25 (Sun, 25 Aug 2024)

  Changed paths:
    M parseAPI/CMakeLists.txt
    M parseAPI/h/CFGModifier.h
    M parseAPI/src/CodeSource.C
    M parseAPI/src/IA_IAPI.C
    A parseAPI/src/IA_riscv64.C
    A parseAPI/src/IA_riscv64.h
    M parseAPI/src/SymbolicExpression.C

  Log Message:
  -----------
  Add RISC-V ParseAPI


  Commit: 2e44471391a448e0dae492ea80a00629aee3f535
      https://github.com/dyninst/dyninst/commit/2e44471391a448e0dae492ea80a00629aee3f535
  Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx>
  Date:   2024-08-25 (Sun, 25 Aug 2024)

  Changed paths:
    A dataflowAPI/rose/SgAsmRiscv64Instruction.h
    M dataflowAPI/rose/conversions.h
    A dataflowAPI/rose/semantics/DispatcherRiscv64.C
    A dataflowAPI/rose/semantics/DispatcherRiscv64.h
    M dataflowAPI/rose/semantics/Registers.C
    M dataflowAPI/rose/semantics/Registers.h
    M dataflowAPI/rose/semantics/SymEvalSemantics.C
    M dataflowAPI/rose/semantics/SymEvalSemantics.h
    M dataflowAPI/src/RoseImpl.C
    M dataflowAPI/src/RoseInsnFactory.C
    M dataflowAPI/src/RoseInsnFactory.h
    M dataflowAPI/src/SymEval.C
    M dataflowAPI/src/SymbolicExpansion.C
    M dataflowAPI/src/SymbolicExpansion.h
    M dataflowAPI/src/convertOpcodes.C
    A external/rose/riscv64InstructionEnum.h
    M external/rose/rose-compat.h

  Log Message:
  -----------
  Implement RISC-V DataflowAPI base code


Compare: https://github.com/dyninst/dyninst/compare/ed426a226feb%5E...2e44471391a4

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