[DynInst_API:] [dyninst/dyninst] d36550: Add the memory-management registers

[Tim Haines <noreply@xxxxxxxxxx>]

  Branch: refs/heads/thaines/gdt_regs
  Home:   https://github.com/dyninst/dyninst
  Commit: d36550cc4fb88226a2bb6655067e59aeb4e94be1
      https://github.com/dyninst/dyninst/commit/d36550cc4fb88226a2bb6655067e59aeb4e94be1
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M common/h/registers/x86_64_regs.h
    M common/h/registers/x86_regs.h
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add the memory-management registers

The processor provides four memory-management registers (GDTR, LDTR,
IDTR, and TR) that specify the locations of the data structures which
control segmented memory management. See Section 2.4 in Volume 3 of
the Intel 64 and IA-32 Architectures Software Developerâs Manual from
June 2021 for details.


  Commit: a2469f4eb49f01141baae7a8373d333211d460b4
      https://github.com/dyninst/dyninst/commit/a2469f4eb49f01141baae7a8373d333211d460b4
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M common/h/registers/x86_64_regs.h
    M common/h/registers/x86_regs.h
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add mxcsr

This is the SSE Control Status Word register. The AMD64
ABI doc says it's 128 bits, but it's actually 32.


  Commit: 43956d6354cb3e74705c819ab965a73b287d7166
      https://github.com/dyninst/dyninst/commit/43956d6354cb3e74705c819ab965a73b287d7166
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M common/h/registers/x86_64_regs.h
    M common/h/registers/x86_regs.h
    M common/src/registers/MachRegister.C

  Log Message:
  -----------
  Add x87 control and status word registers


Compare: https://github.com/dyninst/dyninst/compare/d36550cc4fb8%5E...43956d6354cb