[DynInst_API:] [dyninst/dyninst] 30f08e: Clean up and improve documentation of x86_64 regis...

[Tim Haines <noreply@xxxxxxxxxx>]

  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: 30f08e7b85fa9f3524676691d36bb21723a3d7f5
      https://github.com/dyninst/dyninst/commit/30f08e7b85fa9f3524676691d36bb21723a3d7f5
  Author: Tim Haines <thaines.astro@xxxxxxxxx>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M common/h/registers/x86_64_regs.h
    M common/src/registers/MachRegister.C
    M dataflowAPI/src/SymEvalPolicy.C

  Log Message:
  -----------
  Clean up and improve documentation of x86_64 registers (#1630)

* Improve comments for register lengths

* Separate MMX/3DNow! and x87 register lengths and categories

The MMX* registers are only the lower 64 bits of the st* ones.

* Fix x86_64 subrange mappings in MachRegister::getROSERegister

The values in the two namespaces are not the same.

* Improve comments for EFLAGS fields

* Use symbolic names for the segment register base IDs

* Add missing flag1 from RFLAGS

* Add missing flag3 from RFLAGS

* Add missing flag5 from RFLAGS

* Add missing flagc from RFLAGS

FLAGC is the lower bit of the I/O Permission Level field.

* Add missing flagd from RFLAGS

FLAGC is the upper bit of the I/O Permission Level field.

* Add missing flagf from RFLAGS

* Add missing Virtual-8086 mode (VM) rFLAGS field

* Add conversion to ROSE register for Resume Flag

* Add conversion to ROSE register for Nested Task flag

* Add missing Alignment Check/Access Control (AC) RFLAGS field

* Add missing Virtual Interrupt Flag (VIF) RFLAGS field

* Add missing Virtual Interrupt Pending (VIP) RFLAGS field

* Add missing ID Flag (ID) RFLAGS field

* Fix avx-512 opmask size.

It's 64 bits, not 128.

>From Intel(R) 64 and IA-32 Architectures Software Developerâs Manual
June 2021

15.6.1 OPMASK Register to Predicate Vector Data Processing
  The opmask is a set of eight architectural registers of size
  MAX_KL (64-bit).

* Rename OCT to XMMS

This makes it consistent with the names used for the other vector
extensions.

* Add missing subranges in MachRegister::getROSERegister

* Preserve register number in getBaseRegister

* Clear whole subrange byte for GPRs in getBaseRegister