[DynInst_API:] [dyninst/dyninst] f8ae92: Add Initial support for Analyzing Indirect Control...

[noreply@xxxxxxxxxx]

  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: f8ae92029312a1c9350ec81df9ee10cdba9dcdc7
      https://github.com/dyninst/dyninst/commit/f8ae92029312a1c9350ec81df9ee10cdba9dcdc7
  Author: bbiiggppiigg <bbiiggppiigg@xxxxxxxxx>
  Date:   2021-04-04 (Sun, 04 Apr 2021)

  Changed paths:
    M common/h/amdgpu_op_table.h
    M common/h/amdgpu_vega_sys_regs.h
    A dataflowAPI/rose/SgAsmAmdgpuVegaInstruction.h
    M dataflowAPI/rose/conversions.h
    M dataflowAPI/rose/semantics/BaseSemantics2.C
    A dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C
    A dataflowAPI/rose/semantics/DispatcherAmdgpuVega.h
    M dataflowAPI/rose/semantics/Registers.C
    M dataflowAPI/rose/semantics/Registers.h
    M dataflowAPI/rose/semantics/SymEvalSemantics.C
    M dataflowAPI/rose/semantics/SymEvalSemantics.h
    M dataflowAPI/src/AbslocInterface.C
    M dataflowAPI/src/ExpressionConversionVisitor.C
    M dataflowAPI/src/RoseImpl.C
    M dataflowAPI/src/RoseInsnFactory.C
    M dataflowAPI/src/RoseInsnFactory.h
    M dataflowAPI/src/SymEval.C
    M dataflowAPI/src/SymbolicExpansion.C
    M dataflowAPI/src/SymbolicExpansion.h
    M dataflowAPI/src/convertOpcodes.C
    M external/rose/amdgpuInstructionEnum.h
    M external/rose/rose-compat.h
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/InstructionDecoder-amdgpu-vega.C
    M instructionAPI/src/amdgpu_opcode_tables.C
    M parseAPI/CMakeLists.txt
    M parseAPI/src/IA_IAPI.C
    M parseAPI/src/IndirectAnalyzer.C
    M parseAPI/src/JumpTableFormatPred.C
    M parseAPI/src/JumpTableFormatPred.h
    M parseAPI/src/Parser.C
    M parseAPI/src/SymbolicExpression.C

  Log Message:
  -----------
  Add Initial support for Analyzing Indirect Control Flow on Amdgpu Vega (#979)

* this patch should fix most of the compile warnings

* add dependency to scc

* add support for negate and equal to zero op, and chopoff overflowed bits in constant_ast

* fix readRegister to use the actual reg size instead of fixed 64

* add support for scc

* fix the instruction semantics to include scc in their computation

* remove left over x86 cases in RoseInsnAmdgpuVegaFactory::massageOperands

* remove left over arm registers and function handles

* revert the use of printf back to parsing_printf

* revert back to use parsing printf

* comment out debug message

* fix the problem of zeroing out x86_64 constant asts with zero width

* patch noly 32 bit positive integer

* should fix the logic in simplifying constant ast

* add dummy entries to avoid buffer overflow

* fix ast simplification logic on ppc64

* fix a bug in extractOP that might genereate wrong value for constant of size 64