Branch: refs/heads/capstone_integration
Home: https://github.com/dyninst/dyninst
Commit: c170c8cf2549bf99a8a692c6d4cae8d3cda7bc00
https://github.com/dyninst/dyninst/commit/c170c8cf2549bf99a8a692c6d4cae8d3cda7bc00
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-15 (Sun, 15 Sep 2019)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
e_No_Entry should be invalid instruction
Commit: 48de92d8bb862f27b686863b8377f0df4b0d0d29
https://github.com/dyninst/dyninst/commit/48de92d8bb862f27b686863b8377f0df4b0d0d29
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M instructionAPI/src/InstructionDecoder-Capstone.C
Log Message:
-----------
Fix Result_Type for immediate operands
Commit: 2359707397bb2aca55d2f7d24bfa77396fb5ee90
https://github.com/dyninst/dyninst/commit/2359707397bb2aca55d2f7d24bfa77396fb5ee90
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M instructionAPI/src/Instruction.C
Log Message:
-----------
Do not decode operands for INVALID opcode
Commit: 2dfdb68720bc7cdc2b26c24f4c0ace1cc27b144a
https://github.com/dyninst/dyninst/commit/2dfdb68720bc7cdc2b26c24f4c0ace1cc27b144a
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M instructionAPI/CMakeLists.txt
A instructionAPI/src/InstructionDecoder-Capstone-x86.C
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
Log Message:
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The implicity register conversion between 32-bit and 64-bit does not work.
Add explicit x86 32-bit register conversion from Capstone to Dyninst.
Split Capstone x86 code into a separate file to reduce compilation time
Commit: e723bed54600987b8a1765e2da3f7d0870186827
https://github.com/dyninst/dyninst/commit/e723bed54600987b8a1765e2da3f7d0870186827
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M instructionAPI/src/InstructionDecoder-Capstone-x86.C
Log Message:
-----------
Handle implict read & written registers
Commit: 29fcdce3b5a1cf95bb1aede5a1c0fc686f9f0a2f
https://github.com/dyninst/dyninst/commit/29fcdce3b5a1cf95bb1aede5a1c0fc686f9f0a2f
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M instructionAPI/src/InstructionDecoder-Capstone.C
M instructionAPI/src/InstructionDecoder-Capstone.h
Log Message:
-----------
Allow changing decoding architecture at run time
Commit: 257219b0bafd317ea421c884769ea5188d790bce
https://github.com/dyninst/dyninst/commit/257219b0bafd317ea421c884769ea5188d790bce
Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
Date: 2019-09-16 (Mon, 16 Sep 2019)
Changed paths:
M dataflowAPI/src/RoseInsnFactory.C
M parseAPI/src/IA_IAPI.C
Log Message:
-----------
Delete unnecessary assert and handle implicit operand for call instruction to ROSE
Compare: https://github.com/dyninst/dyninst/compare/03e3f7a43b1a...257219b0bafd
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