[DynInst_API:] [dyninst/dyninst] 7b1511: Template for adding instructions

[Xiaozhu Meng <mxz297@xxxxxxxxx>]

  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: 7b1511943e76cdef96b9c7e7ede4989805965d52
      https://github.com/dyninst/dyninst/commit/7b1511943e76cdef96b9c7e7ede4989805965d52
  Author: Benjamin Welton <welton@xxxxxxxxxxx>
  Date:   2018-09-20 (Thu, 20 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Template for adding instructions


  Commit: 1707147ae4e3f6f78aa0eba5952bf45fbbd7793a
      https://github.com/dyninst/dyninst/commit/1707147ae4e3f6f78aa0eba5952bf45fbbd7793a
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-20 (Thu, 20 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  added power operations, stopped on pg491 of the manual page, lxvll


  Commit: 1d4fc85ec0ff17ab3d14941253a9f114c7731439
      https://github.com/dyninst/dyninst/commit/1d4fc85ec0ff17ab3d14941253a9f114c7731439
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  P492-523


  Commit: 6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca
      https://github.com/dyninst/dyninst/commit/6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
   lxvx (P492, a slash in the memory map and two numbers are included)
	 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
	 stxssp (P501, VRS)
	 stxv (P507, new keyword DQ)
	 xsabsqp (P512, 0 in it)

new keywords included:

	-included new keywords "XS", it should be the storing version of "XT")
	-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
	-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)


  Commit: 5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6
      https://github.com/dyninst/dyninst/commit/5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Log Message:
  -----------
  Merge branch 'power_vector' of github.com:dyninst/dyninst into power_vector


  Commit: 2c8113207782d5f032271773403e78be0e977bde
      https://github.com/dyninst/dyninst/commit/2c8113207782d5f032271773403e78be0e977bde
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
   lxvx (P492, a slash in the memory map and two numbers are included)
				 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
				 stxssp (P501, VRS)
				 stxv (P507, new keyword DQ)
				 xsabsqp (P512, 0 in it)

new keywords included:

	-included new keywords "XS", it should be the storing version of "XT")
	-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
	-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)


  Commit: 0a3c9f6730e67eed51a9335b95863650a4844027
      https://github.com/dyninst/dyninst/commit/0a3c9f6730e67eed51a9335b95863650a4844027
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-27 (Thu, 27 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  09/27/2018 New opcodes added

p523-576(not including p576)

skipped:
nothing

new:
  -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25
  -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log.
  -new keyword included: VRS
  -lxvx: page 492, a slash inside the extened opcode.two entries in the opcode table are included: 31-268 & 31-300


  Commit: 7f04267bcb623d12e846c68d815d30b41d72a513
      https://github.com/dyninst/dyninst/commit/7f04267bcb623d12e846c68d815d30b41d72a513
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-27 (Thu, 27 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h

  Log Message:
  -----------
  09/27/2018 New opcodes added

p523-576(not including p576)

skipped:
nothing

new:
  -third level opcodes: 60-347-(16/17), 63-804-(0), 63-836-(1/2/9/10/17/20/22/25
  -new extended opcodes (opcode 60/61/63), added on 09/25 but was not included in the last log.
  -new keyword included: VRS
  -lxvx: page 492, two entries for this instruction(a slash inside the extened opcode).31-268 & 31-300


  Commit: d947f0abecb00a570387487b92d5ba40f4a3b9e3
      https://github.com/dyninst/dyninst/commit/d947f0abecb00a570387487b92d5ba40f4a3b9e3
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxxxxxxx>
  Date:   2018-10-02 (Tue, 02 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Opcode conflict detected, new opcodes added

p576-690(include but skipped)

skipped:

  -xsrqpi & xsrqpix, P634, two instructions sharing the same opcode, differentiated by EX bit
  -xssqrtsp, P644, xssqrtsp has the exact same opcode with xscmpgtdp (P526)
  -xvcmpgtdp, P668, has exact the same opcode with xsrdpic(P628)
  -xvcmpgtsp, P670, has exact the same opcode with xssqrtdp(P641)
  -xvcvspsxws, P686, has exact the same opcode with xsminjdp(P589)
  -xvcvspuxws, P690, has exact the same opcode with xsmincdp(P587)

new keywords included:
  -P653, included DCMX
  -P636, included RMC, two bit from 21th, always companied with an R bit in the 15th bit.
  -new third level opcode 60-475


  Commit: b19e347b97d61c054e2071b605d4ad03da05c961
      https://github.com/dyninst/dyninst/commit/b19e347b97d61c054e2071b605d4ad03da05c961
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxx>
  Date:   2018-10-11 (Thu, 11 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Note for implementation added, XX3 formants in opcode 60 revised, new opcodes added

Revised:
  - opcode with XX3 formats: extended opcode are expanded from 21-28 to 21-29,
	with last bit treated as 0 and 1 respectively
  - The instructions with Rc bits, included Rc in the extended opcode,
	treated the instructions with Rc=0 and Rc=1 as different opcodes.

	new:
	-xvtstdcdp (P760): DCMX field is chopped into 3 parts. May be a special case in implementation.
	-**new Keyword: UIM:
	   field 12-15 immediate field (xxextractuw,xxinsertw (P766))
	   field 14-15 immediate field (xxspltw (P774))
	  //I think UIM should be modified to a certain expression to show what exact bits are for UIM
	-new Keyword: SHW:
	   field 22-23 specify a shift amount in words
   skipped:
	    -xxpermdi (P773), three arbitrary digits
	    -xxsel (P773), XX4 form
	    -xxsldwi (P774), three arbitrary digits


  Commit: 63c134011b66628f18fd98be82575ab881e41572
      https://github.com/dyninst/dyninst/commit/63c134011b66628f18fd98be82575ab881e41572
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxx>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.


  Commit: c5932d2d07b88b3d487059c31067df198b2834bd
      https://github.com/dyninst/dyninst/commit/c5932d2d07b88b3d487059c31067df198b2834bd
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxx>
  Date:   2018-10-16 (Tue, 16 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h

  Log Message:
  -----------
  10/16 Revision of instructions in Chapter 7

Implementation Notes:
  1. For opcode 57, 58, ext opcode resides in 30-31 bit.
  2. For opcode 61 (111101), the ext opcode resides in 29-31 bit or 30-31 bit,
     depending on whether 30-31 bit is 01. (Manual page 1194)
  3. For the instructions with RMC and R, R is always at the 15th bit.
  4. For opcode 60, the Rc bit is at the 21th bit.

new:
  - Flag bit EX (31th bit), (P634)

left to be entered:
  - stv(P492) & stxv(P507) , with DQ(RA) pattern.
  - In opcode 60, two with XX3 format and 3 arbitrary bits and one with XX4 format.


  Commit: a32481a4c1917f59b8cabcb6e51e1f3e4d988a7b
      https://github.com/dyninst/dyninst/commit/a32481a4c1917f59b8cabcb6e51e1f3e4d988a7b
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-10-18 (Thu, 18 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/InstructionDecoder-power.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Start to integrate new power opcodes


  Commit: 2764bf716497bf884f078177e6fa07d4b35accd7
      https://github.com/dyninst/dyninst/commit/2764bf716497bf884f078177e6fa07d4b35accd7
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxx>
  Date:   2018-10-18 (Thu, 18 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  10/18 Opcode from Chapter 6

Summary of Changable fields:
  UIM:
	  12-15:
		4-524 vspltb
		4-525 vextractub
		4-589 vextractuh
		4-653 vextractuw
		4-717 vextractd
		4-781 vinsertb
		4-845 vinserth
		4-909 vinsertw
		4-973 vinsertd
		13-15:
		4-588 vsplth
    14-15:
		4-652 vspltw

  Rc bit:
		for opcode 4: always 21th bit

	ext opcode for opcode 4:
    26-31: 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 59, 60, 61, 62, 63

	new:
	  Keyword SIM, 11-15 bits
    Keyword SHB, 22-25 bits
		third-level opcode: 4-1538-x


  Commit: 42934a133f021ffb070ac0500fac9fca5ceb9f03
      https://github.com/dyninst/dyninst/commit/42934a133f021ffb070ac0500fac9fca5ceb9f03
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-10-19 (Fri, 19 Oct 2018)

  Changed paths:
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/InstructionDecoder-power.h

  Log Message:
  -----------
  Adding multiple items for Power 8 instruction decoding

1. VSR registers
2. Decoding for several operand fields
3. Decoding for extended op 60


  Commit: e0b47787f00797171ceded23427c0b4abd25dfcc
      https://github.com/dyninst/dyninst/commit/e0b47787f00797171ceded23427c0b4abd25dfcc
  Author: Yuhan Xie <xie75@xxxxxxxx>
  Date:   2018-10-23 (Tue, 23 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  10/23
Chapter 6

new:
    keyword CY, 21th bit
    keyword ST, 16th bit
    keyword SIX, 17-20
    keyword DRM, 18-20
    keyword RM, 19-20
    (ST and SIX always show up together)
    keyword PS, 22th bit

Summary of Changable fields:
		UIM:
		11-15:
		   4-906 vctuxs,
		   4-970 vctsxs,

	  12-15:
	     4-524 vspltb
	     4-525 vextractub
	     4-589 vextractuh
	     4-653 vextractuw
	     4-717 vextractd
	     4-781 vinsertb
	     4-845 vinserth
	     4-909 vinsertw
	     4-973 vinsertd

		4-588 vsplth 13-15

		4-652 vspltw 14-15

		Rc bit:
		  for opcode 4: always 21th bit

		6-bit(26-31) ext opcode for opcode 4:
		   32-47, 59-63


  Commit: aad240c45fae9e395bc0ec8537128af225d073d7
      https://github.com/dyninst/dyninst/commit/aad240c45fae9e395bc0ec8537128af225d073d7
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/InstructionDecoder-power.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Finish most of the Power 8 VSX instruction decoding


  Commit: f0c9b431833129bf288742724968154565961776
      https://github.com/dyninst/dyninst/commit/f0c9b431833129bf288742724968154565961776
  Author: Xiaozhu Meng <mxz297@xxxxxxxxx>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/InstructionDecoder-power.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Merge pull request #498 from dyninst/power_vector

Vector instruction support on Power and recycled opcode


Compare: https://github.com/dyninst/dyninst/compare/1d7826aedb12...f0c9b4318331
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