[DynInst_API:] [dyninst/dyninst] ad1d2e: Fixing save of GPR to verify liveState and not def...

[Sasha Nicolas <sasha@xxxxxxxxxxx> (arm1)]

  Branch: refs/heads/arm64/feature/relocation
  Home:   https://github.com/dyninst/dyninst
  Commit: ad1d2efbb864ca63eac88920891cfa6feaf9752f
      https://github.com/dyninst/dyninst/commit/ad1d2efbb864ca63eac88920891cfa6feaf9752f
  Author: Sasha Nicolas (arm1) <sasha@xxxxxxxxxxx>
  Date:   2018-06-05 (Tue, 05 Jun 2018)

  Changed paths:
    M dyninstAPI/src/codegen-aarch64.C
    M dyninstAPI/src/dynProcess.C
    M dyninstAPI/src/inst-aarch64.C

  Log Message:
  -----------
  Fixing save of GPR to verify liveState and not defined registers bitArray.
Fixing alignment of save and restore of FPR for base tramp.
Add assert for SPR save not to have null register.
Fix long branch generate to get a scratch register.
Ssaving X30 for every emitCall.


  Commit: 5a88f21a246d5015c4de326a611239ef362fe34b
      https://github.com/dyninst/dyninst/commit/5a88f21a246d5015c4de326a611239ef362fe34b
  Author: Sasha Nicolas (arm1) <sasha@xxxxxxxxxxx>
  Date:   2018-06-05 (Tue, 05 Jun 2018)

  Changed paths:
    M dyninstAPI/src/Relocation/Springboard.C
    M dyninstAPI/src/addressSpace.C
    M dyninstAPI/src/codegen-aarch64.C
    M dyninstAPI/src/inst-aarch64.C
    M proccontrol/src/linux.C
    M proccontrol/src/process.C

  Log Message:
  -----------
  Fixing generateAddSubImmediate for ADD and SUB instructions. Wrong bits and wrong opcode were being set.
Fixing generation of save and restore for registers using the SP register. Previous instruction didn't update SP.
Fixing int_process bug in create().


Compare: https://github.com/dyninst/dyninst/compare/711ed271ccbf...5a88f21a246d
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