[DynInst_API:] [dyninst/dyninst] 555078: Add instruction semantics for extsw on powerpc


Date: Thu, 29 Mar 2018 14:28:38 -0700
From: Xiaozhu Meng <mxz297@xxxxxxxxx>
Subject: [DynInst_API:] [dyninst/dyninst] 555078: Add instruction semantics for extsw on powerpc
  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: 5550789e38a867152ce49b105601773ae9f909bd
      https://github.com/dyninst/dyninst/commit/5550789e38a867152ce49b105601773ae9f909bd
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherPowerpc.C

  Log Message:
  -----------
  Add instruction semantics for extsw on powerpc


  Commit: 0c31798ed8390ddb1861f95123d2844e58fa6410
      https://github.com/dyninst/dyninst/commit/0c31798ed8390ddb1861f95123d2844e58fa6410
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M parseAPI/src/Parser.C

  Log Message:
  -----------
  When dealing with overlapping instructions, we should align block as
soon as possible, correctly split blocks, anc create new fall-through
edges


  Commit: afac5cfec4048dcd3a1bc86e0bf365ab1fa98cd6
      https://github.com/dyninst/dyninst/commit/afac5cfec4048dcd3a1bc86e0bf365ab1fa98cd6
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M dyninstAPI/src/syscallNotification.C

  Log Message:
  -----------
  Need to flush trap mapping table into the mutatee after instrumentation for registering callbacks


  Commit: 0c4b469950e00483bbabce457cb9c2a5970bc3d4
      https://github.com/dyninst/dyninst/commit/0c4b469950e00483bbabce457cb9c2a5970bc3d4
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M instructionAPI/src/Instruction.C

  Log Message:
  -----------
  ppc32 and ppc64 should use the same formatter


  Commit: 87339181970dff789f52991800b880ac49f1db7c
      https://github.com/dyninst/dyninst/commit/87339181970dff789f52991800b880ac49f1db7c
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M dwarf/src/dwarfFrameParser.C

  Log Message:
  -----------
  Should continue to check other CIEs when we cannot find FDE in one of the CIE


  Commit: 3cfbf940aa9679d8b48feeffcb6e24358ebbda1c
      https://github.com/dyninst/dyninst/commit/3cfbf940aa9679d8b48feeffcb6e24358ebbda1c
  Author: Xiaozhu Meng <xmeng@xxxxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M parseAPI/src/Block.C

  Log Message:
  -----------
  When checking whether an address is consistent with instructionsin a
block, first check whether the address is within the block


  Commit: 1b437a72cfda787a5d16a3c8759ef72be6907ad9
      https://github.com/dyninst/dyninst/commit/1b437a72cfda787a5d16a3c8759ef72be6907ad9
  Author: Xiaozhu Meng <mxz297@xxxxxxxxx>
  Date:   2018-03-29 (Thu, 29 Mar 2018)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherPowerpc.C
    M dwarf/src/dwarfFrameParser.C
    M dyninstAPI/src/syscallNotification.C
    M instructionAPI/src/Instruction.C
    M parseAPI/src/Block.C
    M parseAPI/src/Parser.C

  Log Message:
  -----------
  Merge pull request #446 from mxz297/powerpc_and_loop

Fixes for testsuite failures on powerv7 and block boundary aligning for overlapping instructions


Compare: https://github.com/dyninst/dyninst/compare/e7b69e6c3eab...1b437a72cfda
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