Date: | Thu, 22 Dec 2016 09:46:33 -0800 |
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From: | Sunny Shah <shah28@xxxxxxxx> |
Subject: | [DynInst_API:] [dyninst/dyninst] 6ab930: Issue #262 ([ARMv8 Decoding] FMUL instruction cann... |
Branch: refs/heads/att_syntax Home: https://github.com/dyninst/dyninst Commit: 6ab9302f30081548a14f14b48f026da4319ad9ac https://github.com/dyninst/dyninst/commit/6ab9302f30081548a14f14b48f026da4319ad9ac Author: Sunny Shah <shah28@xxxxxxxx> Date: 2016-12-22 (Thu, 22 Dec 2016) Changed paths: M instructionAPI/src/InstructionDecoder-aarch64.C Log Message: ----------- Issue #262 ([ARMv8 Decoding] FMUL instruction cannot have size:q = '10') SIMD vector x-indexed instructions that use the 'sz' field should be invalid for a certain combination of the values of the 'sz', 'L' and 'Q' fields. |
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