Date: | Wed, 21 Dec 2016 12:34:48 -0800 |
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From: | Sunny Shah <shah28@xxxxxxxx> |
Subject: | [DynInst_API:] [dyninst/dyninst] bdd6c9: Issue #258 ([ARM Decoding] FMUL instructions canno... |
Branch: refs/heads/att_syntax Home: https://github.com/dyninst/dyninst Commit: bdd6c9754a96818faf12218bbaf65d305c41fad8 https://github.com/dyninst/dyninst/commit/bdd6c9754a96818faf12218bbaf65d305c41fad8 Author: Sunny Shah <shah28@xxxxxxxx> Date: 2016-12-21 (Wed, 21 Dec 2016) Changed paths: M instructionAPI/src/InstructionDecoder-aarch64.C Log Message: ----------- Issue #258 ([ARM Decoding] FMUL instructions cannot have 'size:L' == '11') A subset of instructions in the SIMD scalar x-indexed element category should be invalid if bit 0 of the 'size' field and the 'L' field are both 1. |
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