[DynInst_API:] [dyninst/dyninst] dd48e7: Issue #220 (Zero register should have sizing, eith...

[Sunny Shah <shah28@xxxxxxxx>]

  Branch: refs/heads/att_syntax
  Home:   https://github.com/dyninst/dyninst
  Commit: dd48e72c1520f9d7bac94005f130f701d2c14b6e
      https://github.com/dyninst/dyninst/commit/dd48e72c1520f9d7bac94005f130f701d2c14b6e
  Author: Sunny Shah <shah28@xxxxxxxx>
  Date:   2016-11-08 (Tue, 08 Nov 2016)

  Changed paths:
    M common/h/dyn_regs.h
    M common/src/dyn_regs.C
    M dataflowAPI/rose/semantics/SymEvalSemantics.C
    M instructionAPI/src/InstructionDecoder-aarch64.C

  Log Message:
  -----------
  Issue #220 (Zero register should have sizing, either XZR or WZR)

64-bit zero register is renamed from ZR to XZR.

This commit also allows the XZR register to appear in STP instructions.