Branch: refs/heads/bbiiggppiigg/amdgpu-hostcall-multiwave-scratch
Home: https://github.com/dyninst/dyninst
Commit: 0bc2b46ea88eff28c7871b34bf2e47f3ce68cd2e
https://github.com/dyninst/dyninst/commit/0bc2b46ea88eff28c7871b34bf2e47f3ce68cd2e
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M dyninstAPI/src/codegen/codegen-amdgpu.C
Log Message:
-----------
amdgpu: make generateBranch short-jump consistent with modifyJump/Jcc
Fold the S_BRANCH PC+4 correction into wordOffset (disp/4 - 1) and emit it
directly, matching modifyJump/modifyJcc. Pure cleanup; same emitted code.
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
Commit: e4e97632d964cc80c94d7d1ab39f384d45135d1e
https://github.com/dyninst/dyninst/commit/e4e97632d964cc80c94d7d1ab39f384d45135d1e
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M dyninstAPI/src/emit-amdgpu.C
Log Message:
-----------
amdgpu: multi-pack SGPR spill + footprint-sized scratch slot (roadmap 0.3/0.4)
0.4: the SGPR spill packed the callee's clobbered scalars {numbered SGPRs, VCC}
one-per-lane into a SINGLE 64-lane VGPR, silently capping at 62 SGPRs (64 - 2 for
VCC) and corrupting callees above that. Generalize to numPacks =
ceil((nsgpr+2)/64) pack VGPRs (vPack..vPack+numPacks-1), each spilled to its own
dword slot. numPacks==1 reproduces the previous single-pack code exactly.
bumpCallerKdForCallee now reserves numPacks pack VGPRs in the grant (and the
grant/slot bump is unconditional since the spill always runs to preserve VCC).
0.3: scratch spill slot was a hardcoded 256 bytes, overflowing the scratch
aperture for large VGPR/SGPR footprints. Size it per-callee to
private_segment_fixed_size = 4*(numPacks + nvgpr); S_VGPR_SLOT/VGPR_AREA now sit
after the packs.
spillPackLanes() (env DYNINST_PACK_LANES, default 64, clamped <=64) is a test
knob to force numPacks>1 with a small callee. Validated: DYNINST_PACK_LANES=8
forces numPacks=5 (5 pack VGPRs to distinct scratch slots) -> PASSED; default
path PASSED at N=1024 (vectoradd) and divergent N=256.
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
Commit: d716e6940c78e32b5d0430189d780c19f57e0a25
https://github.com/dyninst/dyninst/commit/d716e6940c78e32b5d0430189d780c19f57e0a25
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M dyninstAPI/src/amdgpu-gfx908-details.C
M dyninstAPI/src/amdgpu-gfx908-details.h
M dyninstAPI/src/emit-amdgpu.C
Log Message:
-----------
amdgpu: pass immediate call arguments (roadmap 2.1)
emitCall no longer requires operands.empty(). For each compile-time Constant
operand it materializes the value into the AMDGPU function-CC argument register
(VGPR args from v0: arg i -> v(i)) via a new emitVop1Imm helper (v_mov_b32 vN,
<32-bit literal>). The materialization runs after the register spill-save and the
exec-restore-for-call and before the s_swappc, so overwriting v0.. (already
saved/restored by the VGPR spill) is safe; the value is uniform per wave (a
callee may readfirstlane it to a scalar). HIP cannot express inreg/SGPR
arguments, so a plain int lands in v0; only immediate (Constant) operands are
supported for now (assert otherwise).
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
Commit: d6605121f05502ff570a09044d86eb5e7cce5acc
https://github.com/dyninst/dyninst/commit/d6605121f05502ff570a09044d86eb5e7cce5acc
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-07-07 (Tue, 07 Jul 2026)
Changed paths:
M amdgpu-hostcall-poc/examples/test_amdgpu_instrument/test_amdgpu_instrument.C
M amdgpu-hostcall-poc/hostcall_lib/hostcall_lib.cpp
M amdgpu-hostcall-poc/hostcall_lib/hostcalls.h
M amdgpu-hostcall-poc/launcher/hostcall_launcher.cpp
Log Message:
-----------
amdgpu-hostcall-poc: parameter-passing demo for roadmap 2.1
Snapshot the PoC-side changes that exercise dyninst's new immediate call-argument
passing:
- hostcalls.h: HC_OP_WRITE_ID opcode + int32_t arg mailbox field
- hostcall_lib.cpp: hc_write_id(int id) wrapper (readfirstlane -> mailbox.arg)
- hostcall_launcher.cpp: service HC_OP_WRITE_ID -> "[gpu] site N"
- test_amdgpu_instrument.C: insert hc_write_id(BPatch_constExpr(siteIndex))
at each write point instead of the nullary hc_write
End-to-end: the per-site immediate is materialized into v0 by emitCall and logged
per wave (trace shows site 0..7; N=256 -> 32 lines; data PASSED).
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
Compare: https://github.com/dyninst/dyninst/compare/7c8812ee6a41...d6605121f055
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