Branch: refs/heads/bbiiggppiigg/amdgpu-hostcall-multiwave-scratch
Home: https://github.com/dyninst/dyninst
Commit: 409a7b3da95d9c744b362154b05f761eeecb494a
https://github.com/dyninst/dyninst/commit/409a7b3da95d9c744b362154b05f761eeecb494a
Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
Date: 2026-07-06 (Mon, 06 Jul 2026)
Changed paths:
M dyninstAPI/src/emit-amdgpu.C
Log Message:
-----------
amdgpu: spill to real hardware scratch off FLAT_SCRATCH (drop s[94:95] + lane math)
The env-gated DYNINST_SPILL_SCRATCH path previously reconstructed a per-wave
address in the s[94:95] SGPR pair and spilled with global_store + manual mbcnt
per-lane offset math ("fake scratch"). Switch it to genuine scratch_store/
scratch_load off FLAT_SCRATCH:
- Prologue sets FLAT_SCRATCH (s102:103) = flat_scratch_init + wave_offset, the
compiler-exact per-wave base (byte-identical to the compiler's own
s_add_u32 flat_scratch_lo, s6, s9). s102:103 is a SPECIAL register outside the
allocatable pool, so it costs zero GP SGPRs. wave_offset (s9) is consumed here.
- Spill via scratch_store/load_dword off, vN, s94 (seg=1). gfx908 forbids
both-operands-off scratch addressing (verified via llvm-mc), so SADDR must be a
register - but with the base in FLAT_SCRATCH it is just a constant 0 in s94
(s_mov s94,0 in the prologue): one SGPR instead of the s[94:95] pair.
- Hardware provides per-lane swizzle, so vAddr and all mbcnt/shl lane math are
gone; VGPR grant drops from vAddr+2 to vAddr+1; per-register slot shrinks from
a 256B stride to 4B (SGPR pack @0, v_i @4+i*4).
Global-buffer path unchanged as the default. Validated N=64/128/256/512 PASSED
with linear per-wave hostcall scaling; disassembly confirms flat_scratch setup,
scratch_* spills, and no residual s[94:95] add or mbcnt ops.
Co-Authored-By: Claude Opus 4.8 <noreply@xxxxxxxxxxxxx>
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